What should I pay attention to when determining the value of the input capacitor of a step-down DC/DC converter?
In essence, the recommended components listed on the data sheet for each IC and their values should be used as reference. Moreover, depending on the DC voltage applied to a capacitor, the effective capacitance of the capacitor is different, and so the characteristic curve provided by the manufacturer indicating the relationship between DC voltage and capacitance should be referenced to select a capacitor for which an effective capacitance equal to that of the recommended component can be ensured. At the same time, recommendations for grade and other parameters should be observed.
Please explain how to determine the capacitance value of an input capacitor.
From the standpoint of stable operation of a power supply IC, the products and values recommended by the data sheet should first be considered. When it is also necessary to reduce input ripple voltages and spike noise for EMC measures, capacitors should also be studied in accordance with frequency bands to be used and the required impedance characteristics.
The capacitance value of a ceramic capacitor changes depending on the DC bias characteristic. Does the impedance characteristic also change as a result?
As the actual capacitance declines with a DC bias, the resonance point shifts to higher frequencies, and so the impedance characteristic also changes.
As a way of taking into account the DC bias characteristic of a ceramic capacitor, would it be correct to select a size for which the change in capacitance is small in the voltage range of actual use?
That would be correct. However, capacitors with small capacitance changes are larger in size. When space or other issues arise, after considering the capacitance change due to the DC bias characteristic, a capacitor can be selected the actual capacitance of which is equivalent to the recommended value.
When selecting an input capacitor, what would be reasons for choosing a ceramic capacitor with a capacitance value which shows low impedance?
In general, the lower the capacitance of a ceramic capacitor, the higher is the self-resonant frequency, so that the device functions as a capacitor up to higher frequencies. There are mainly two types of frequency components in the switching operation of a DC/DC converter: the switching frequency (ranging from hundreds of kHz to several MHz), and the switching rise/fall frequency (from 100 MHz). In order to suppress power supply fluctuations at the latter in particular, 100 MHz and up, a ceramic capacitor with a low capacitance is necessary.
What would be a reason for connecting an electrolytic capacitor and a ceramic capacitor in parallel at the input?
It will probably depend on the design specifications of the set, but a large-value electrolytic capacitor is used for the purpose of delaying attenuation of the input voltage when the set power supply is turned off, whereas a ceramic capacitor has a small ESR and so is used to supply charge when there are sudden current changes, as with switching currents.
When the capacitance of an input ceramic capacitor has changed due to the DC bias characteristic, should the impedance characteristic be reexamined as well?
Attenuation of the capacitance due to the DC bias characteristic causes the resonance frequency and other impedance characteristics to change accordingly as well. The capacitor manufacturer should be asked for the impedance characteristics for DC biasing, and devices selected on this basis, or else a MLCC should be used with a high rated voltage and a value sufficient to accommodate drops in capacitance at the voltage of use due to the DC bias characteristic.
When positioning a small-capacitance ceramic capacitor for input bypass and a large-value capacitor, which should be placed closer to the IC?
The bypass capacitor should be closer to the IC. This capacitor must deal with large current changes per unit time, and if it is at a distance from the IC, the parasitic inductance of the wiring is increased, making it less effective.
When using decoupling capacitors to deal with multiple frequencies, is it better to use multiple capacitors for the respective frequencies, or should a single capacitor be used with the value selected to deal with the frequencies collectively?
Also, are there any problems with adding multiple capacitors?
It is recommended that multiple capacitors be used for different frequencies. As for problems, if multiple capacitors having self-resonant frequencies that are far apart are used, antiresonances may occur between those frequencies, and there are concerns that noise characteristics may be worsened at the antiresonance frequencies. Also, when arranging multiple capacitors, it is preferable that capacitors with higher self-resonant frequencies (mainly small-value capacitors) be placed closer to the IC; if instead capacitors with higher self-resonant frequencies are positioned further away, the line inductance to the capacitors will cause the self-resonant frequency to shift to lower frequencies, and the intended characteristics may not be obtained.
When selecting a capacitor, in many cases the ESR value does not appear on the data sheet for an electrolytic capacitor. How should I go about examining the ESR value?
For various details, including the ESR, the capacitor manufacturer should be consulted.
Please explain what needs to be considered when using electrolytic capacitors as input or output capacitors.
It is important to confirm that the input voltage and output voltage ripple waveforms are within the allowed range. In many cases the ESR is large compared with ceramic capacitors. Also, it is important to note that the temperature characteristic is inferior to that of ceramic capacitors.
Why is an input capacitor necessary?
An input capacitor is necessary for the stability of the input voltage.
Please explain the disadvantages when the inductance of an inductor is increased in order to reduce the ripple current ΔIL of a DC/DC converter, and conversely, the advantages of reducing the inductance.
Problems when the L value is increased include the need to increase the capacitance of the output capacitor in order to maintain load response performance, and the fact that the inductor size is increased.
When the L value is reduced, there is the problem that the ripple voltage is increased. When using an extremely small L value, the ripple current is increased, so that it is necessary to confirm that the overcurrent detection value of the power supply IC is not reached during normal operation.
If the L value of an inductor is set to a high value in anticipation of the maximum load current, and then in actual operation the output current is smaller than the maximum load current, do any problems with operation and characteristics arise? That is, I would like to know whether there are any adverse effects if the L value is made too large.
If a value deviates considerably from the recommended value, there are cases in which the phase compensation must be adjusted. Because the power supply frequency characteristics change with the L value, it is necessary to confirm that there are no problems with stability and responsiveness. Moreover, for some ICs the inductance value is specified, and in such cases the specified value should be used.
When the L value of an inductor is changed from the recommended value, in some cases the efficiency may be improved, but are there any trade-offs?
There are cases in which, by setting an inductance value to be higher than the recommended value, the efficiency under light loading can be improved. As trade-offs, the frequency characteristics and ripple current magnitude change, and so the device operation and behavior must be studied and verified thoroughly.
What adverse effects may occur if an inductor L value is too large?
Possibilities include worsening of load transient response performance and a larger inductor size. In addition, depending on the method of IC control, limits on the L value may be imposed; if an inductor with an L value outside this limits is used, control loop stability may be compromised.
When an output current that is actually to be used is about half the output current value of a data sheet application circuit or the like, would it be better to modify the L value of the inductor for actual use?
It would be better to use the inductance value of the data sheet application circuit and values within the range of recommended inductance values. For example, if the actually used current were 1/100, the inductance would be dramatically increased to an unrealistic value. Considering these matters, although it is not the case that large values can never be substituted for smaller ones, waste and excess tend to appear, and so a power supply with an output current near the current to actually be used should be selected.
When increasing the inductance of the output inductor, what would be a reason for also increasing the capacitance of the output capacitor?
To complement changes in the response to changes in the output load current.
What might be adverse effect of increasing the inductance value to reduce the output ripple voltage?
Adverse consequences of increasing the L value include the need to increase the capacitance of the output capacitor in order to maintain load transient response performance, and the larger size of the inductor.
Please explain the disadvantages when the inductance of an inductor is increased in order to reduce the ripple current ΔIL.
An inductor with a large inductance is physically large, and tends to be more expensive.
What must be checked when increasing the L value of an inductor in a recommended circuit?
When the inductance value is increased, if the inductor is of the same size, the rated current may be smaller, and therefore it must be confirmed that the rated current is sufficient. Where operation is concerned, the load transient response performance is worsened, and so voltage fluctuations during load fluctuations must be checked. Also, there are ICs for which a change in inductance value causes a change in frequency characteristics. The frequency characteristics of voltage-mode control ICs in particular must be checked, to confirm that the output voltage is stable with respect to load current transients. For current-mode ICs, when the inductance range is specified, if an inductor in this range is not selected, operation instability may occur.
When selecting an inductor for a DC/DC converter, what influence do the DCR and ACR have?
They affect the power supply efficiency. The larger the DCR, the greater is the loss due to the inductor average current and the DCR. And a larger ACR means that the loss due to the inductor ripple current and the ACR is increased.
Are there any problems with using an IC with the inductor current in discontinuous mode?
There are no problems, but there is the disadvantage that, if the load current changes sharply, the responsiveness is worsened compared with continuous mode.
What is the reason for the different slopes of the rise and fall of the ripple current of an inductor?
This is because of the different voltages at the two ends of the inductor. When the high-side switch is on, the potential difference Vin-Vout is applied to the inductor. When the high-side switch is off, the potential difference 0 V-Vout is applied to the inductor.
If the L value is increased or the output capacitor is made larger in order to suppress the ripple current, will these things affect phase compensation?
If the output L and C values are increased (changed), there will be an effect on the frequency (phase) characteristics of the power supply circuit. However, if the output L and C values are within the upper- and lower-limit ranges specified by the data sheet, then by adjusting the values of the phase compensation components, stable operation can be achieved.
Please explain how to determine the inductor value when the output current of a DC/DC converter has a certain range, such as for example 0.5 A to 3.0 A.
Components are selected based on the maximum current. For currents within the range example given, calculations should be performed for a current of 3 A.
When an IC has an overcurrent detection function, must the output inductor saturation current be set equal to or greater than the overcurrent detection value?
If there is a load current exceeding the saturation current of the inductor, the ripple current increases more than anticipated, and the overcurrent detection value is reached. Hence it is recommended that the saturation current value be set to the overcurrent detection value or higher.
What is the reason for setting the ripple current ΔIL of an inductor to between 30 and 40% of the output current?
If ΔIL is set to 30 to 40% of the output current, a balance can be achieved between power supply performance parameters such as efficiency, load transient response, and stability.
Is magnetic saturation of an inductor related to temperature?
When the core material is ferrite, magnetic saturation occurs readily at high temperatures. When the material is metallic, magnetic saturation does not occur easily due to the material characteristics.
Please explain matters of importance when selecting an inductor.
The inductor must be selected so that the switching current peak does not exceed the DC bias current rating of the inductor.
When selecting an inductor, a device should be selected with a sufficient margin relative to the calculated value of the saturation current. But what should be regarded as a "sufficient" margin?
In general, the margin should be about 20% or so, but ultimately the various characteristics provided on the data sheet should be considered carefully.
The inductor selection example includes the expression "start from a xx μH inductor with a saturation current of at least xx A", but how should the device finally be selected?
Ultimately, this decision must be made after using actual equipment to confirm the phase characteristics and load transient response characteristics.
About how much of a margin should be provided in the DC bias current of an inductor?
Basically, if the current is at or below the allowable current stipulated by the inductor manufacturer, then there will be no problem with respect to stable IC operation.
About how much of a decline in the inductance at the current to be used should be expected due to the DC bias characteristic of an inductor?
The allowed current value with respect to L value attenuation in the DC bias characteristics are determined for the inductor, and so selections should be made so as to remain within this current.
About how much of a margin should there be for the inductor saturation current?
In general, the margin is considered to be about 20% or so, but ultimately the various characteristics provided by the data sheet should be considered carefully when making this determination.
Is it true that in general, if an inductor is used at or below the rated current, magnetic saturation does not occur? Also, is the current value at which magnetic saturation occurs listed on the data sheet, or must actual measurements be performed?
If the inductor is used at or below the rated current, magnetic saturation will not occur. The value can be actually measured, or it should be okay to consult the inductor manufacturer.
What should I consider to be the limit to the rate of decrease in percent indicated by the DC bias characteristic of an inductor that I am considering using?
The DC bias characteristic is described by Isat, and the rate of decrease differs among inductor manufacturers and products, at values such as 20% or 30%. Hence the specifications of an inductor to be used should be studied carefully before making a decision.
ESR (Equivalent series resistance)
When a capacitor with a large ESR such as an electrolytic capacitor is used, apart from the ripple voltage, what other problems might there be?
There are cases in which the frequency characteristics change. It is necessary to check the phase margin and confirm operation stability.
Why does an output ripple voltage occur?
In a switching power supply, switching (repeated on/off operation) and an inductor are used, and so a ripple current flows. The ripple voltage occurs because of this ripple current and the ESR of the output capacitor.
Is it general practice to use a design such that the output ripple voltage is low?
The magnitude of ripple voltages that are allowed differs depending on the device and circuit to which power is to be supplied. For example, when used as the power supply of an amplification circuit for sensors and minute signals or as the power supply of low-voltage microcomputers and FPGAs, designs that reduce the ripple voltage are generally used.
When the output current of a DC/DC converter has a range such as for example 0.5 A to 3.0 A, how does one determine the output capacitor value?
Component selection is based on the maximum current. For the example given of the current range, calculations should use a current of 3 A.
When increasing the inductance of an output inductor, what would be a reason for increasing the capacitance of the output capacitor as well?
To compensate for changes in response with respect to changes in the output load current.
What are points to be noted when determining the capacitance of the output capacitor of a step-down DC/DC converter?
Basically, the recommended components and their values listed on the data sheet for the IC should be taken as reference. Moreover, depending on the DC voltage applied to the capacitor, the effective capacitance of the capacitor will be different, and so the characteristic curve provided by the manufacturer indicating the relationship between DC voltage and capacitance should be considered to select a capacitor that can ensure an effective capacitance equal to that of the recommended component. At the same time, components should conform to grades and other parameters.
Please provide a specific example of determination of a reasonable capacitance value for an output capacitance.
The details differ with the IC and the conditions of use, and so the values on the IC data sheet should be consulted and, in essence, adjustments should be made based on confirmation using actual equipment, according to the desired output ripple voltage and load transient response characteristics.
Why is an output capacitor necessary?
An output capacitor is needed for stability of the output voltage when fluctuations in the load current occur.
The inrush current that occurs upon power supply startup in a DC/DC converter can be reduced, perhaps, but can it be eliminated?
The inrush current flows when charge is supplied to the output capacitor, and so cannot be eliminated. However, by slowing the rise time of the power supply, the peak value of the inrush current can be lowered sufficiently.
I would like to know about the mechanism of startup failure relating to soft starts.
Startup failures occur when the output capacitance value is too great. The output capacitance is charged with electric charge during a soft start time period, but if the output capacitance is too large, charging may not be completed during the soft start time period, so that the output voltage has not risen sufficiently, and if an overcurrent or short-circuit protection condition applies, these may be actuated to result in startup failure.
I understand that a long soft start time period due to a large output capacitor value may result in startup failure, but can one perform calculations to determine whether startup failure will occur?
Standard calculation methods are provided on the data sheets of ICs, and in essence, these should be used. In the end, actual equipment should be used to confirm operation and make judgments accordingly.
What kinds of demands should be used to determine the soft start time period?
It should be determined so as to satisfy the demand specifications for the device to which power is to be supplied. However, if the soft start time period is too short, attention must be paid to the rush current (Irush) into the output capacitor. In the case of an IC with an overcurrent protection function, care must be taken to ensure that the rush current (Irush) on startup does not trigger overcurrent protection activation. In order to suppress the rush current, Cout must be made small and the startup time lengthened.
To about what value should I set the soft start time period?
In essence, the user should set this according to the conditions of use. Depending on the device to be powered, the rise time may be specified. If the soft start time period is set to a short value, attention must be paid to inrush currents (when present).
An inrush current at the input may cause a fuse to blow. What countermeasures should be considered, such as regarding soft start, output capacitor, input capacitor, and the like?
It may be that the inrush current is greater than anticipated, and so such measures as using a longer soft start time period, and decreasing the capacitance of the capacitor in the circuit section where the inrush current is occurring, may be used.
Is there an upper limit to the externally set soft start time period?
This differs with the IC, and so you will need to make inquiries in each case.
⑤Output voltage setting resistor
Because the resistor used to set the output voltage is also a load, if the resistance value is small, the wasted output current increases and efficiency falls. Is it better to make this value as high as possible?
A higher value is better in the sense that the wasted output current is reduced, but if the resistance value is too high, the FB line impedance is high, and the circuit becomes susceptible to external noise, so caution is necessary.
How is the output voltage tolerance determined?
Basically, in the case of an adjustable-output-voltage type device using an external resistor, it is determined by the tolerance of the reference voltage accuracy of the IC and the tolerance of the resistor that sets the output voltage. For a fixed-output-voltage type device, it is as specified in the IC data sheet.
I would like to know the equation for calculating the output voltage tolerance.
In the case of an adjustable-output-voltage type device with an external resistor, the parameters are the tolerance of the IC reference voltage accuracy and the tolerance of the output voltage setting resistor. Calculation basically involves using the combination of tolerances in the equation for the output voltage setting.
Is it necessary to consider the effect of the FB pin current when choosing the resistor to set the output voltage?
Strictly speaking, there is such an effect, but the resistance value should be of the order (number of digits) of the component value recommended on the data sheet. The output voltage is determined as a voltage ratio; if the recommended value is 24 kΩ + 30 kΩ, then the setting should be adjusted using a resistance of kΩ order.
Is a recommended value for the capacitance of a bootstrap capacitor listed on data sheets?
It is listed on data sheets.
The recommended value for a bootstrap capacitor is 0.1 μF. Should I select a capacitor taking into account the DC characteristics, AC characteristics, and temperature characteristics so that the minimum capacitance is 0.1 μF, or should I simply select a 0.1 μF capacitor?
A capacitor for which an effective capacitance of 0.1 μF can be secured should be selected.
Is there an equation to calculate the capacitance of a bootstrap capacitor?
Could a MOSFET be destroyed due to a mistake in selecting a bootstrap capacitor?
A MOSFET probably could not be destroyed as the result of a mistaken selection of a bootstrap capacitor. If the capacitance is too great, adequate charging is not possible, so that Vgs would be insufficient; if the capacitance is too small, the electric charge that charges the capacitor would be inadequate, so that Vgs would again be insufficient. As a result, turn-on of the high-side MOSFET would be delayed, and depending on the extent to which Vgs was inadequate, it might not be possible to turn the MOSFET on at all. As a result, it is likely that the output voltage would drop, or that operation would stop.
When the capacitance of a bootstrap capacitor is too large, depending on the performance of the internal power supply, the rise of the boot voltage is delayed. Why does this occur?
The boot voltage is determined by the amount of electric charge flowing into the capacitor. Hence when ability of the internal power supply to provide current is limited, the increase of the boot voltage is slowed. It is recommended that a value close to the recommended value of the data sheet be used.
In an application where the duty cycle changes considerably, how should I think about the capacitance of the bootstrap capacitor?
If the capacitance of the capacitor is the recommended value, there should be no problems even when the duty cycle changes. However, if the capacitance is too much larger than the recommended value of the data sheet, the on duty becomes large, and charging times are shortened, possibly resulting in malfunctions, so proper caution is needed.
Why must the capacitance of a bootstrap capacitor be set substantially larger than the gate capacitance of the high-side MOSFET?
The gate of the high-side MOSFET is driven by the charge accumulated on the bootstrap capacitor. If the gate capacitance of the high-side MOSFET were larger, charge sufficient for driving could not be supplied, and the time until MOSFET turn-on would be lengthened.
Does selection of the external capacitor for a bootstrap circuit affect the maximum duty cycle (max duty)?
In general, equations for the maximum duty cycle do not include capacitor parameters. However, if the capacitance is too large, there could be an effect. The recommended value of the data sheet should be used for the capacitor of a bootstrap circuit.
If the capacitance of the bootstrap capacitor of a synchronous rectification DC/DC converter with an upper/lower Nch MOSFET configuration is set to be far greater than the recommended value, for example ten times greater, would any problems result?
If the capacitance is too large, the current supply ability of the internal power supply of the IC would not be adequate for charging, and it might not be possible to turn on the MOSFET adequately.
How should I calculate the lower limit for the capacitance of the bootstrap capacitor of a synchronous rectification DC/DC converter with an upper/lower Nch MOSFET configuration?
Recommended values for the bootstrap capacitor vary with the IC; at ROHM, we use evaluations to confirm operation down to one-half the recommended value. However, thorough checking with actual equipment is ultimately necessary. Please check with the data sheet in each case.
Bootstrapping drives the Nch high-side MOSFET, but how should the voltage to charge the capacitor be secured?
There are many ICs designed to use an IC operation power supply generated within the IC, but the data sheet should be checked in each case.
There is no indication of the threshold value of the MOSFET VGS for an IC with an internal output MOSFET. How can I judge whether bootstrapping is correct or not.
The parameters of internal MOSFETs are not made public. Please use the value recommended on the data sheet for the bootstrap capacitor.
Do problems occur if the bootstrapping voltage is too high?
If the rated voltage of the IC is exceeded, failure is possible. Proper operation results if the value for the bootstrapping capacitor recommended on the data sheet is used.
FRA (frequency response analyzer)
Is there a method of easily checking the phase margin and gain margin even when one cannot use an FRA (frequency response analyzer)?
Frequency characteristics are somewhat equivalent to the load transient response, and so if an FRA cannot be used, an electronic load or the like can be employed to perform load transient response experiments for the expected load. When the phase margin is insufficient, ringing can be generated in the load transient response waveform to observe unstable waveforms. It is possible to determine whether waveforms are stable and whether phase compensation is properly performed. The application note at the following link should be consulted. https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/fra_phase_margin_appli-e.pdf
If I do not own an FRA (frequency response analyzer), is there some other method for checking the response characteristics?
You can apply the expected current fluctuations to the output, use an oscilloscope to check the resulting voltage fluctuation waveform, and if there is no sign of oscillation or sustained ringing in the output voltage, you can conclude that the response characteristic is more or less normal.
Is it correct to assume that frequencies indicated on the horizontal axis of a Bode plot acquired by an FRA (frequency response analyzer) are switching frequencies of the DC/DC converter?
The horizontal axis of a Bode plot indicates the frequency of an applied signal. The Bode plot of an FRA represents the gain and phase of the voltage that passes through the circuit within the IC and has returned again to the analyzer when a sine wave set in the FRA is applied to the IC feedback section while sweeping through frequencies.
Is it correct that the gain attenuation in a Bode plot obtained using an FRA (frequency response analyzer) is due to wiring resistance, and the phase lag is the delay due to the wiring distance?
The main cause of gain attenuation and phase lag is a delay in signal propagation in the feedback loop circuit.
When an FRA (frequency response analyzer) cannot be used, is there some other way of generating a Bode plot?
A Bode plot can be obtained by separating the output and the voltage division resistor for voltage setting (feedback resistor), inputting a sine wave signal on the feedback resistor side, using an oscilloscope to monitor the signal from the output, and plotting the amplitude difference and phase difference between the input signal and the output signal at each frequency. However, reading off figures from the monitored waveforms is difficult, and so this is not a very realistic method.
Is there some method for measuring the phase margin and the gain margin that does not require use of an FRA?
Trends can be predicted to some degree from calculations and simulations, but in the end it is necessary to use an FRA with actual equipment for confirmation. As one means of confirming stability of operation without using an FRA, transient response characteristics can be evaluated, and a rough judgment can be made from signs of oscillation in the output voltage and from the state of ringing.
When a Bode plot analysis using an FRA (frequency response analyzer) or the like cannot be performed to examine unwanted oscillations arising due to insufficient phase margins or gain margins, is there a method for identifying positive-feedback oscillations from the oscillation frequency? For example, can it be considered that the switching frequency is an oscillation frequency, or the like.
Oscillations that occur when there are insufficient phase or gain margins are oscillations at frequencies lower than oscillations due to switching frequencies. Whether or not oscillations are occurring can be determined by using an oscilloscope to determine whether or not there are any anomalies (oscillations) in the output voltage or switching waveform.
Phase compensation resistor and capacitor
When an FRA (frequency response analyzer) cannot be used, if the resistor and capacitor for phase compensation are set to values calculated using equations, will it be reasonable that oscillation or other problems do not occur?
As a rule, the values may be set to calculated values without issue, but the types and characteristics of the components actually used, as well as the layout of the board wiring, may exert influences. Hence it is necessary to use actual equipment to thoroughly confirm that the output voltage and the switching waveform are stable.
Regarding phase margin adjustments using a capacitor and resistor connected to the ITH pin, if the resistor is increased from the normal value of 9.1 kΩ to for example 27 kΩ, what happens to the phase and gain margins?
Both the phase margin and the gain margin will tend to be worse.
When the resistance is increased, the feedback loop zero point moves to lower frequencies. The zero point raises the gain, and so movement of the zero point to lower frequencies causes the crossover frequency to move to higher frequencies. The phase lags as the frequency moves higher, and consequently, due to broadening of crossover frequencies and the phase lag at higher frequencies, both the phase margin and the gain margin are worsened.
I think that the values of the phase compensation resistor and capacitor at the ITH pin should be determined according to degree of stability, but what can I do to improve the load transient response characteristic?
If the crossover frequency is set high, the load transient response characteristic will be improved. However, there is a tendency for the phase margin to be reduced, so caution is required.
Is it correct to assume that if the phase compensation resistor at the ITH pin is reduced from the proper value, the load transient response will worsen (Vout convergence will be slower)?
If the resistance is reduced, the crossover frequency will be lower, so the load transient response will tend to be worse.
How are the equations to determine the values of the phase compensation resistor and capacitor at the ITH pin derived?
These appear on IC data sheets. Please refer to the data sheet for details.
When adjusting phase compensation, if the resistor at the ITH pin is set to the recommended value and the capacitance of the capacitor is increased until anomalous oscillations cease, then the value deviates considerably from the recommended value. In this case, is it better to also adjust the resistance value?
To deal with this situation, the resistance is reduced, but ordinarily, operation is essentially stable at or near the value recommended by the data sheet. The inductor value and output capacitor value should also be checked to ensure that they are not greatly different from the recommended values. If operation is not stable for components near the recommended values, some other factors may be involved, including the layout.
If the resistance value for phase compensation is fixed and the value of the capacitor for phase compensation is changed, what happens to the phase and the gain?
When the capacitor for phase compensation is modified, both the zero and the pole frequencies change, and so it is not possible to generalize about what will happen. The behavior also depends on internal parameters of the IC being used. For some ICs, ROHM Solution Simulator and SPICE models have been made public, and so it is recommended that simulations first be performed to check behavior.
When the capacitor and resistor used for phase compensation are to be adjusted, which should be adjusted first?
When making adjustments, the resistance value should be changed first. By modifying the resistance value, the zero-cross frequency changes directly.
Often the calculated values for the resistor and capacitor for phase compensation do not coincide with actual existing values. In such cases, should one choose a value that is smaller than or larger than the calculated value?
The value closest to the calculated value should be selected. It makes no difference whether the value is larger or smaller than the calculated value.
In phase compensation adjustment, when the capacitance of the capacitor is increased, how does the Bode plot change?
When the capacitance of the capacitor is modified, because various parameters exert an influence, it is impossible to state what will change in general terms.
Moreover, the internal characteristics of the IC being used and external components such as inductors are also affected.
Please explain in detail the equations for calculation of the capacitor and resistor for phase compensation. Do the calculated values result in the optimal state with respect to phase margin and gain margin?
Details of the equations are given on the IC data sheet, which should be consulted. Calculated values are theoretical values, however, and it is recommended that calculations be confirmed using actual equipment.
How should tuning of the resistor and capacitor at the ITH pin be performed in order to improve load transient response characteristics?
By raising the zero-cross frequency, the response characteristic is improved. If the resistance is increased, the zero-cross frequency rises, and so the circuit can be adjusted in the direction of improved response characteristics. However, if the resistance is increased too much, the phase margin disappears, and oscillation may occur. In this case, the capacitance is reduced, and this adjustment secures a phase margin. When it is necessary to improve the transient characteristics as well, an output capacitor could be added to reduce fluctuations in the output voltage. When an output capacitor is added, the frequency characteristics also change, and so it is necessary to again check the frequency characteristics and study whether the ITH pin resistor and capacitor need adjustment.
When using simulations to evaluate feedback loop stability, can I be provided with an IC model (SPICE etc.)?
PSpice models for a number of ICs are made public on websites. In the case of an IC without a model published on the internet, please inquire about models for each case.
Is it possible to simulate phase margins and gain margins?
Analyses can be performed using a SPICE model for the IC. Moreover, simulations can also be performed by using the "Simulation" of "Frequency Domain" for the relevant IC in "IC Solution Circuit" of the "ROHM Solution Simulator" provided free of charge on the ROHM website. It should be understood that SPICE models and Solution Circuits have not been prepared for all ICs.
Do you provide web-based simulations or the like to check phase margins and gain margins on the web?
The "ROHM Solution Simulator" is provided free of charge on the ROHM website. It can be used simply by registering at My ROHM. Upon clicking on "Simulation" of "Frequency Domain" for the relevant IC in "IC Solution Circuit", the simulation is started. However, there are ICs for which a Solution Circuit has not been prepared.
Is there a method for simulating phase margins and gain margins?
SPICE models have been prepared for some ROHM ICs; these can be used to execute simulations. In addition, the ROHM Solution Simulator, accessible from the ROHM home page, can be used.
For DC/DC converters, a phase margin of 45 degrees or greater, and a gain margin of -10 dB or lower, are used as standard values. Why are these values used?
These values are used because they balance appropriate response speed and stability. If the phase margin and gain margin are inadequate, ringing or other unstable waveforms appear as load transient response waveforms. And, if too much emphasis is placed on stability in a design with reduced bandwidth, response is worsened and the load transient response characteristics are adversely affected.
I understand that the ITH pin can be used for phase compensation, but can the gain be adjusted?
The DC gain within the IC is fixed and cannot be adjusted from the outside.
I'd like to know what is important when checking the phase margin and gain margin, and standard values for margins.
For the phase margin, the phase at the frequency at which the gain is 0 dB is measured, and for the gain margin, the gain at the frequency at which the phase is 0 degrees is determined, and the margins for each of these are studied. Representative values are 45 degrees or greater for the phase margin, and for the gain margin, -10 dB or lower.
Do the waveforms in anomalous oscillation states differ when there is no margin for the gain only, when there is no margin for the phase only, and when there is no margin for either the phase or the gain?
The states are essentially the same with respect to disorder of the on duty.
There is no difference in terms of anomalous operation deviating from expected values.
What conditions are used to set the crossover frequency of the frequency characteristics?
The frequency is set within a range in which a phase margin is secured; about 1/20 of the oscillation frequency is a standard value.
How do I calculate the crossover frequency of the frequency characteristics?
Equations are provided on the data sheets of the different power supply ICs. The data sheet for the IC should be consulted.
Do the phase margin and the gain margin change depending on the magnitude of the output capacitor Cout?
They do change. The changes also depend on the IC, but when Cout is smaller, the crossover frequency is shifted higher, and the phase margin and gain margin are reduced.
In phase compensation, the crossover frequency is generally calculated based on the switching frequency; what is the reason for this?
Due to the dead time system, the phase lags by 360 degrees at the switching off duty frequency. That is, in the frequency band surrounding the switching frequency, it is essentially certain that stability cannot be secured and that oscillation will occur. Hence the switching frequency is frequently used as one index to calculate the crossover frequency.
How should I calculate the crossover frequency, which is needed when calculating the resistor value for phase compensation?
The crossover frequency is a value set by the user. In general, good results are often obtained by setting it to from 1/10 to 1/20 of the switching frequency.
Is the crossover frequency, which is necessary when calculating the resistor value for phase compensation, indicated on the data sheets for power supply ICs or the like?
The crossover frequency is a value set by the user. In general, good results are often obtained by setting it to from 1/10 to 1/20 of the switching frequency.
What might one imagine to be the worst conditions for the phase margin?
The worst conditions will differ depending on the temperature characteristics of the capacitor used and the like, and depending on changes in the effective capacitance due to bias effects.
The phase margin is measured at the input voltage, load conditions, and usage temperature range to measure the worst value.
Does the value of the output feedback resistor (voltage dividing resistor) affect the phase or gain?
It has no particular influence.
In the case of a power supply IC without a phase compensation pin, what can be done about phase compensation?
In the case of an IC without a phase compensation pin, it may be possible to adjust the frequency characteristics through the output capacitor and inductor. However, this depends on the IC, and users should make individual inquiries.
If the load continuously passes a constant current, is there no need to worry about load transient response characteristics?
Even when the load is a constant current, the output fluctuates at the beginning of the flow of the load current and at other times, and so it is probably necessary to check the degree of stability through waveforms. Moreover, if the crossover frequency is low (that is, response characteristics are poor), overshoot of the output voltage on startup may be large, and so once again, waveforms should be checked.
There are cases in which ceramic capacitors are connected in parallel to a resistor connected on the output side of a voltage dividing resistor (feedback resistor) for setting the output voltage. Why?
By connecting ceramic capacitors in parallel, a phase advance can be imparted. By means of such a phase advance, a larger phase margin can be secured, and response can be improved.
What kinds of factors cause changes in the delay time that occurs in the feedback loop of a power supply circuit?
In essence, the main factor is the signal propagation delay in the feedback loop circuit.
What are the temperature, input voltage, output voltage, and load conditions to be used when evaluating the phase margin and gain margin?
Basically, it is good policy to employ the conditions of use that are assumed for the actual equipment, or to conduct evaluations based on the same conditions as the operation specifications for the actual equipment.
Are there criteria to use in evaluating load transient response characteristics?
This is a direct evaluation for signs of oscillation or ringing given load current fluctuations that are expected to occur for the set to be used. Moreover, because fluctuations in the output voltage occur in load response, it is also necessary to determine whether or not the fluctuations are within the allowed fluctuation range for the output voltage of the actual equipment.
Should the metal trace from the dividing resistor for setting the output voltage to the FB pin be made thin or thick? There should be almost no current flowing, so it seems that rather than worrying about wiring resistance, it should not be made thicker than needed, in order to reduce the parasitic inductance and capacitance.
In general, this wiring is almost always made narrower than power lines. In addition to parasitic inductance and capacitance, narrower wiring is also effective in the sense of reducing the effect of crosstalk from surrounding circuits.
For remote sensing purposes, I want to locate an output voltage for feedback close to the load device, which is far from the power supply IC. In this case, the wiring to the FB pin will be long, and a separate LC filter not normally included in a feedback loop is included. How can I deal with this?
Check the actual frequency characteristics (phase, gain margins) of the feedback loop including the LC filter to confirm stability. It will also be necessary to observe the output voltage waveform during load fluctuation of the actual set, to ensure that continuous ringing or other signs of oscillation do not appear in the output voltage.
What kinds of problems might occur owing to a ground that includes circuits in the vicinity of a DC/DC converter? In particular, I'd like to know about measures for dealing with the PSRR (power supply rejection ratio) and common-mode noise.
If the ground for circuits near the DC/DC converter is not appropriate, normal operation may not be possible, desired characteristics may not be obtained, and unwanted noise could occur. In such cases, the PSRR may be lower than the IC value (specification), or the common-mode noise level may be high. As countermeasures, it is recommended that the ground be made more robust by providing vias near the IC, increasing the ground area, and the like.
Is it better to separate the power GND and the signal GND?
In essence, it is better that they be separated.
Are there any other high-impedance lines besides the FB line?
In general, apart from the FB pin, the SS (soft start) pin and the ITH pin and the like are high-impedance lines. This differs with the type of IC, and so must be checked in each case.
Why is it that I need to be careful about crosstalk in the case of a high-impedance line?
The main causes of crosstalk are currents (noise) induced by inductive coupling due to metal trace inductance and capacitive coupling between metal traces. Even when the same current is induced, voltages are higher in a line with higher impedance, and the chances that this may lead to circuit malfunction are greater, so more caution is required.
If the feedback resistance from the output to the FB pin is high, there is a greater chance of the circuit being affected by crosstalk; but what about the influence of a bias input current at the FB pin?
Naturally, if the feedback resistance value is too high, the bias input current will have an effect. A bias current mainly affects voltage precision. Where crosstalk is concerned, often there are AC fluctuations, causing ripple increases and abnormal oscillation.
Why is it that crosstalk occurs more readily when the impedance of the feedback path from the output (FB line) is high?
When noise propagates due to capacitive coupling from nearby wiring or the like, the higher the line impedance, the higher is the resulting noise voltage. In other words, crosstalk effects tend to result.
Output voltage setting resistor
Where on the output line should the output voltage setting resistor (feedback resistor) be connected? I would also like to know the reasons for this. Shouldn't the voltage (waveform) be different depending on the place in the output line--the inductor part, output capacitor part, load, and so on?
It is recommended that this be connected as close to the output capacitor as possible, separately from the path in which the load current flows (from the inductor to the output capacitor). This is because, even for the same output node, a voltage drop occurs due to the PCB parasitic impedance between the inductor and the output capacitor.
Soft start pin capacitor
When the wiring resistance up to the capacitor at the soft start pin cannot be ignored, should it be calculated using the time constant? What equation is used to do this?
If the source current of the soft start pin is constant, then when the source current is isrc, the capacitance of the soft start pin capacitor is Css, the resistive component up to Css is Rss, and the soft start pin voltage is Vss, then Vss is given as follows.
Vss＝isrc/Css*time Rss * isrc
When Vss is applied as a feedback voltage reference, the output voltage rises such that the feedback voltage becomes Vss. When the wiring is so long that the wiring resistance has an effect, there are concerns that malfunctions due to noise may occur, and further study is needed.
In a PCB layout, I understand that the input capacitor should be positioned as close to the IC Vin pin as possible, but about how far away can it be?
There are no strict stipulations, but the farther away it is, the more its effect is weakened. As a reference value based on experience, please consider using 5 mm or less as a rule of thumb.
Please explain which components must be mounted in the same layer as the IC, and which can be mounted on the opposite surface.
It is recommended that components that pass a switching current be mounted in the same layer as the IC. This applies to inductors, input capacitors, output capacitors, and diodes (in the case of non-synchronous rectification). When there is an external switching transistor, it is recommended that the switching transistor also be on the same surface as the IC.
What kinds of peripheral components present no problems with respect to performance or noise even when mounted on the surface opposite the IC mounting surface?
Mounting on the surface opposite the IC mounting surface means using vias, and so there is the effect of the inductance component of the vias. From this it can be said that components that tend not to be on the path of a high-frequency current are comparatively unaffected. More specifically, it is likely that for components other than input or output capacitors, capacitors at internal power supply pins, and bootstrap capacitors, the effect of placement on the surface opposite the IC is relatively small. However, any component can be affected by mounting on the rear side of an inductor, in particular directly below the inductor. Also, apart from components, signal lines can also be affected, so caution is required.
Are there any constraints on the PCB placement of inductors, diodes, and capacitors on the IC output side?
In a step-down DC/DC converter, the greatest caution is needed for input to capacitors. Outputs are switched, and so attention must be paid to interference between switching nodes and other lines.
Is there anything I should be aware of when I place output-side inductors, diodes, and capacitors on the PCB board?
Output switching nodes are noise sources in a circuit at which large currents are switched rapidly, and so there are multiple issues requiring attention, such as wiring and component placement. Where PCB layout is concerned, attention must be paid to the input as well as to the output side. Please refer to the materials relating to PCB layout at the link below. https://techweb.rohm.com/knowledge/dcdc/dcdc_pwm/dcdc_pwm03/2734
An input capacitor is supposed to be positioned very close to the IC, but should I pay attention to the placement of the inductor, output capacitor, or other components?
Because short wiring should be used for switching nodes, the inductor, like the input capacitor, is best located close to the IC. As for the output capacitor, noise can be kept minimal by placement so as to minimize insofar as possible the area of the current loop consisting of the IC SW pin → output inductor → output capacitor → IC PGND (GND) pin.
For what components other than the input capacitor do I have to be careful about placement?
Care is also required in placement of inductors, switching transistors, and diodes (in the case of diode rectification) that are connected to IC switching pins. Component layout and PCB design methods for general-use step-down DC/DC converters are described in the "PCB Layout Method for Step-down Converters" application note at the following URL. https://techweb.rohm.com/document/#dcdc
A SPICE model is available; can it be used with OrCAD 16.0?
When creating SPICE models, OrCAD 17.2-2016 is used; operation in version 16.0 has not been confirmed.
When running a simulation to evaluate stability of a feedback loop, can I obtain a model of the IC (SPICE etc.)?
We have published PSpice models for a number of ICs on our website. In the case of an IC for which a model is not present on the website, please inquire separately.
Is it possible to simulate phase margins and gain margins?
By using a SPICE model for the IC, this analysis is possible. In addition, simulations can also be performed by using the "Simulation" of "Frequency Domain" for the relevant IC in "IC Solution Circuit" of the "ROHM Solution Simulator" provided free of charge on the ROHM website. It should be understood that SPICE models and Solution Circuits have not been prepared for all ICs.
Do you provide web-based simulations or the like to check phase margins and gain margins on the web?
The "ROHM Solution Simulator" is provided free of charge on the ROHM website. It can be used simply by registering with My ROHM. Upon clicking on "Simulation" of "Frequency Domain" for the relevant IC in "IC Solution Circuit", the simulation is started. Please note that Solution Circuit is not provided for all ICs.
Is there a method for simulating phase margin and gain margin?
SPICE models have been prepared for some ROHM ICs; these can be used to execute simulations. In addition, the ROHM Solution Simulator on the ROHM website can be used.
For some types of IC, the switching frequency can be selected; what is the purpose?
In order to expand the freedom of design. If the switching frequency is raised, smaller external inductors can be used, so that board space can be saved. However, efficiency is lower, so that heat generation is increased, and there is the possibility of increased high-frequency noise. The frequency must be determined considering trade-offs between conditions of use and requirements.
What are the drawbacks when raising the switching frequency to reduce output ripple voltages?
Drawbacks when raising the switching frequency include higher noise frequencies, and heat generation due to worsened efficiency.
How should I determine the switching frequency? I also want to know about its relation to noise.
The switching frequency affects the output ripple of a DC/DC converter and the inductor current ripple. The higher the switching frequency, the smaller the resulting ripple, but switching losses tend to be greater, so that there is a trade-off with efficiency and heat. The noise is mainly the spectral noise occurring at multiples of the switching frequency, but lower frequencies result in lower levels of noise in the high-frequency range.
Is there a recommended value for the switching frequency? For example, are higher values better, or are lower values preferred?
In essence, no. The switching frequency affects the efficiency, load transient response, radiated emission, and other parameters, and so must be chosen by the user according to the required power supply specs, the purpose of use, and other factors.
How does one determine the switching frequency?
Power supply ICs with fixed-frequency operation include models in which the switching frequency is fixed internally, and models for which the switching frequency is set by the value of an external component. In devices with frequency modulation operation such as those using PFM, the switching frequency changes with the input/output conditions and the load.
One approach is to raise the switching frequency so that smaller inductors and capacitors can be used. Is there anything that needs to be taken into consideration when determining the frequency?
There are various things to be considered. One is the need to suppress output ripple voltages to a value that can be tolerated by the device being fed power. The output ripple voltage depends on the amplitude of the ripple current flowing in the inductor. The ripple current in the inductor depends on the output inductance and capacitance (LC), and on the switching frequency. Hence optimal devices must be selected, also including inductor and capacitor sizes.
Raising the switching frequency is one way to lower the ripple voltage, but how high should the switching frequency be raised? And what problems might result from a higher frequency?
There is an upper limit to the switching frequency depending on the IC; please refer to the data sheet. Problems with raising the switching frequency include increased heat generation due to poorer efficiency, and increased high-frequency noise.
What should I pay attention to when choosing components assuming transient loading?
Components must be selected considering maximum values, including ripple currents, given the maximum values in the transient loading.
How large a margin should I set for components to be used? I'd also like to know the basis for numerical values.
There is no numerical basis for the margin to be used for components, but from experience and the like, in general there are many cases in which values of 80% or lower are used.
About what amount of withstand voltage derating might I use for input capacitors and output capacitors?
Using a factor of two or so is common practice, taking into consideration external noise. In the case of ceramic capacitors, the DC bias characteristics must also be considered, and this should be given priority while also considering the size and withstand voltage.
Please tell me about countermeasures that can be used to deal with noise emitted by a DC/DC converter.
While this depends on the type of DC/DC converter, one countermeasure that is common to all types is insertion of a CR snubber circuit between the switching pin and GND. One could also put filter circuits on input and output lines.
Adding a snubber circuit is one way to deal with EMI in a DC/DC converter, but are there any methods that do not involve adding circuits or components?
The most fundamental EMI countermeasure is shortening, insofar as possible, the distance over the path of input capacitor → high-side switching transistor → low-side switching transistor → input capacitor.
One method of reducing noise is to insert a resistor into the gate line of the output-stage MOSFET of a DC/DC converter, but do any problems occur when ferrite beads are used?
Ferrite beads are effective for attenuating high frequencies around 100 MHz, but if ferrite beads are inserted into a power line, they may cause malfunctions.
I understand that there are many techniques for reducing output noise from a DC/DC converter; what methods are recommended?
In general, a small-value capacitor is added to lower the impedance at the frequency at which noise appears. For the impedance characteristics of capacitors, it is recommended that design assistance tools provided by the capacitor manufacturers be used.
What should I be careful of when addressing noise that occurs in switching operation under PWM control?
Noise components include noise at frequencies that are multiples of the oscillation frequency, and noise that occurs at the slew rate (inclination) of on/off switching, and so noise countermeasures that correspond to these frequencies will be needed. As a measure to deal with EMI, the input capacitor should be placed as close as possible to the IC input pin.
I understand that overshoot during switch-on is greater or smaller depending on the location of the input capacitor, but for what component can I improve the layout so as to reduce undershoot during switch-off?
It may be possible to improve this with a layout in which the input and output capacitors and the IC ground are in close proximity.
When insertion of an RC snubber circuit to deal with switching noise does not result in adequate noise reduction, is there anything in the PCB layout that I should check?
Switching noise can sometimes be reduced by using the shortest possible loop containing the input capacitor, the IC input pin, and PGND.
What kind of a design takes switching noise into consideration?
In addition to the characteristics of the MOSFETs and diodes used, the amount of switching noise also varies greatly with the PCB layout. Hence for a step-down DC/DC converter, a layout design is necessary that makes the wiring between MOSFETs, diodes (or for synchronous rectification, MOSFETs), and the input capacitor as short as possible.
I would like to know what to watch out for when adding a filter, whether an LC filter or an RC filter, to the output side to address switching noise.
In the cases of both an LC filter and an RC filter, it will be necessary to confirm the extent of attenuation of the output voltage and to ensure that an adequate phase margin and gain margin are secured.
What highly effective countermeasure is there for cases in which switching noise also affects the input side?
As a general measure, there is the method of inserting a ceramic capacitor with optimal capacitance and frequency characteristics between close to the IC input pin and GND, so that the impedance is reduced at the noise frequency.
I am using a snubber circuit to deal with noise; is there some other method for suppressing radiated emission?
Basically, the input capacitor (in particular a bypass capacitor) can be positioned close to the IC input pin, and an inductor with weak magnetic flux leakage can be selected for use.
To deal with noise, a snubber circuit can be added afterward; but should it be added in the initial design stage? I'd also like to know reasons why this might or might not be necessary (frequency, voltage?).
In a DC/DC circuit, a snubber circuit is related to the rising and falling slew rate, and (depending on conditions) is effective for frequencies ranging from tens to hundreds of MHz. However, when considerable noise improvement is needed, resistance losses become extremely large. If a snubber circuit is added improperly, it may mean an appropriate layout cannot be used, so that noise is worsened as a result.
In the case of DC/DC converter ICs with internal power transistors, positioning the input capacitor as close as possible to the IC input pin is highly effective. Hence layout is emphasized more than use of a snubber circuit.
I see circuits in which a damping resistor is inserted at a bootstrap capacitor; is this necessary? How should I decide whether it is necessary?
The reason for inserting a resistor in series with a bootstrap capacitor is often to reduce the slew rate during switching rising in order to reduce noise. If noise is an issue, one can consider adding such a resistor, but the longer rise time will mean that switching loss increases, and so it will be necessary to check the power supply efficiency and temperature increases.
At about what frequencies do ripple and switching noise occur?
Noise is affected by multiples of the switching frequency and the on/off slew rate of switching transistors. For example, if the switching frequency is 1 MHz, ripple will be at 1 MHz, and switching noise will be in a band of several hundred MHz.
When a snubber circuit is to be added afterward to an existing DC/DC board, what kinds of mounting and expansion methods are recommended?
A snubber circuit is added to areas where noise is occurring; in the case of an RC snubber, resistive losses are large, and so the mounting should consider resistor heat generation. Also, while dependent on the frequencies being addressed, if the wiring inductance is large, the effect at higher frequencies is diminished, and so a layout that pays attention to noise will often be more effective.
Why do input ripple voltages and spike noise occur?
Output ripple currents also flow on the input side. Because of these currents and the input capacitor ESR, ripple voltages occur in the input as well. Spike noise occurs due to current changes accompanying turn-on and turn-off of output switching transistors, and to parasitic inductances in current paths. In order to reduce spike noise, parasitic inductances must be made smaller.
Can noise on the input side appear in the output, and conversely, can output-side noise appear on the input side?
While depending on the type and properties of the noise, for some input and output capacitor settings and positions on the PCB, it is possible for noise to propagate from input to output, or from output to input.
Is there a type of IC with less radiated emission?
There are ICs that have slower switching slew rates (the rising and falling speeds of the switching square wave). However, lower efficiency is a countervailing factor. There are ICs that have functions for spreading the switching frequency, so that noise peaks can be suppressed.
When measuring inductor currents, should the wire to be connected to the inductor end be connected to the IC side or to the output capacitor side?
It is connected to the IC side to perform measurements.
I would like to know the specifications of a current probe used to measure inductor current waveforms and of a wire (diameter and length) connected to the inductor ends for such measurements.
In a ROHM example, and taken purely as reference, the current probe used is a Tektronix model TCP0030A. The length of the wire connected to the inductor is the shortest length that can be gripped by the current probe; the wire normally has a conductor diameter of 0.7 mm and an diameter with insulation of about 1.3 mm. When the current value is large, several of the same wire may be used in parallel, or other conditions may be chosen according to the circumstances.
How can an inductor current waveform be observed?
Connect a wire to the inductor end (IC side), and observe it using a current probe.
There is considerable noise (spikes) in measurements of output ripple voltage. Please describe the recommended measurement environment.
Use a passive probe for measurement of both ends of the output capacitor. At this time, the GND lead of the probe is not used, and grounding should be such that the loop area of the measurement points and GND is made as small as possible. Moreover, a probe must be used with a sufficient frequency band relative to the frequency being measured.
What method can be used to ascertain the rising and falling frequency bands of the input current due to switching?
The current flowing to the drain of the switching transistor (MOSFET) must be measured directly, to measure the rise and fall times. If the purpose is to eliminate noise, check for voltage ringing waveforms at the switching pin, and choose a capacitor that can lower the resonance frequency.
It seems that in synchronous rectification, conduction losses are low and therefore efficiency is high; but what about switching losses?
Where switching losses are concerned, there is no great difference between synchronous rectification and diode (non-synchronous) rectification. Hence where efficiency is concerned, it can be said that synchronous rectification is superior.
What is the output ripple voltage of a DC/DC converter?
In a DC/DC converter, a triangular-wave switching (inductor) current is output. this current charges an output capacitor, and so a triangular-wave voltage, due to the output capacitor ESR (equivalent series resistance) × switching current, appears at the output. The amplitude of this voltage is called the ripple (pulsating) voltage.
How much conduction is allowed in the parasitic diode of a MOSFET?
Because this differs depending on the power supply IC and the MOSFET (in the case of an external device), inquiries should be made separately for given models.
Why is it that in general, so few kinds of DC/DC converter ICs incorporating Pch MOSFETs have high-voltage, large-current specifications?
Compared with an Nch MOSFET with the same current and voltage ratings, a Pch MOSFET is larger in size. Hence the IC chip is larger, and so due to the package size and superior performance, more ICs using Nch MOSFETs are used.
Isn't the Ron (on resistance) the same for a Pch MOSFET and an Nch MOSFET which are the same size?
When the device sizes are the same and VGS is the same, Ron is lower for the Nch MOSFET.
What are the advantages of a synchronous rectifying DC/DC converter IC that uses Nch MOSFETs for both the high and low sides in the output stage?
Compared with ICs that use Pch MOSFETs, smaller size is possible for the same performance. Conversely, for a given size, performance is greater. Due to demands for smaller size and higher efficiency in recent years, Nch MOSFET type devices have an inherent advantage.
In synchronous rectification using Nch MOSFETs on both the high side and the low side, why is it that operation at a 100% duty cycle is not possible as with a high-side Pch MOSFET, and that the maximum duty cycle is limited?
In order to drive a high-side Nch MOSFET, the gate voltage must be higher than the drain voltage. For this reason a bootstrap circuit is provided, but in order to charge the chargeup capacitor with electric charge, the low-side MOSFET must be turned on and the switching pin must be low. Because this requires some time, there is a limit to the maximum duty cycle.
Is it correct to assume that, in a synchronous rectifying DC/DC converter IC, when the high side transistor is an Nch MOSFET as opposed to Pch MOSFET, the maximum output voltage for a given input is lower but Ron is smaller, so that less heat is generated by the MOSFET itself?
In the case of an Nch MOSFET, operation at a 100% duty cycle is not possible, so that the maximum voltage that can be output is lower than for Pch MOSFET, and there is the possibility that the difference between input and output voltages may be large. If the MOSFET sizes are the same, it is reasonable to suppose that the Nch MOSFET, with its smaller Ron, will generate less heat; but it is necessary to consider whether other conditions are equivalent.
What disadvantages result when a Pch MOSFET (high side) and Nch MOSFET (low side) are used in the output stage of a synchronous rectifying DC/DC converter IC?
When the Pch MOSFET characteristics are equivalent to those of the Nch MOSFET, the size is increased, so that the IC size is larger.
Light load mode
What is the approximate threshold value for switching into high-efficiency operation in diode rectification under light loading?
The efficiency improvement under light loading may be due to operation in which switching is skipped, or to discontinuous operation in which the current flowing in the inductor is discontinuous. Pulse-skipping operation begins when the load current falls to roughly 1/2 or less of the inductor ripple current IL.
Schottky barrier diode
Must diodes in a diode rectifying DC/DC converter be Schottky barrier diodes?
While they are not mandatory, Schottky barrier diodes have a low forward voltage and short reverse recovery time, and so are recommended due to their superior efficiency.
In relation to selection of Schottky barrier diodes for diode rectification, apart from the reduction in efficiency, does the voltage drop by the amount of the forward voltage:
1) affect the value of the preset output voltage? or,
2) affect the output ripple voltage?
3) Also, is the diode junction capacitance related to DC/DC operation?
The set value for the output voltage is the voltage after switching and smoothing with an LC filter, that is, the voltage fed to the load is generally fed back, and is regulated at the preset voltage, including the voltage drop due to the diode, and so there is no effect on the set value for the output voltage. There is also no effect on the output ripple voltage. The junction capacitance also is generally hardly affected at all.
When using Schottky barrier diodes in a diode rectifying DC/DC converter, what is a rule of thumb for the input voltages that can be used? I have heard that it is better not to use too high a voltage.
The rated voltage of Schottky barrier diodes now on the market is generally up to 200 V. While there are differences depending on the application, generally a margin of from 1.3 to 2 times the input voltage is secured for a power supply. Calculating from this, for a 200 V device, inputs of up to about 100 V should be allowed. There are different policies with respect to margins, and in essence these are considered when making a decision.
Apart from the lower efficiency, does the voltage drop by the amount of the forward voltage of a Schottky barrier diode in a diode rectifying DC/DC converter affect the preset output voltage?
The set output voltage is generally fed back after the switching voltage has been smoothed by an LC filter, and is regulated at the set value, including the drop due to the diode forward voltage, so that there is no effect on the set output voltage.
Please explain matters to be aware of when selecting Schottky barrier diodes for a diode rectifying DC/DC converter.
The rated voltage and forward voltage are the main parameters for selection. The rated voltage must be at least as high as the input voltage. Depending on the PCB layout and the other components used, switching voltage overshoot may occur, rising above the input voltage, and so this must also be considered. The lower the forward voltage, the more losses are reduced, for better efficiency.
In the case of a diode rectifying DC/DC converter, can Schottky barrier diodes only be used externally? Are there ICs which use these diodes internally?
There are ICs with internal Schottky barrier diodes, but because of the somewhat larger switching losses in diodes, most ICs are designed for external diodes.
Discontinuous mode/LC resonance
Where are the L and C of the LC resonance that occurs during discontinuous operation of a diode-rectifying DC/DC converter?
The L is mainly the inductance of the output inductor; the C is the diode parasitic capacitance component.
What should I assume are the effects of resonance during discontinuous operation of a diode-rectifying DC/DC converter?
There are not thought to be any particular effects of this resonance. Ringing is itself a sine wave type phenomenon, and so higher harmonic components do not appear as noise.
Does the LC resonance that occurs during discontinuous mode of a diode-rectifying DC/DC converter pose any problems?
Because control is basically executed such that the preset voltage is output even when LC resonance occurs, no problems arise. However, when there is a load current change causing a shift from discontinuous to continuous operation, the load transient response is slower than during continuous operation, and the change in the output voltage is large.
I would like to know the mechanism of occurrence of LC resonance during discontinuous operation of a diode-rectifying DC/DC converter.
When the output capacitor is charged with electric charge, a current attempts to return to the diode side, but because current does not flow from cathode to anode, charge with nowhere to go causes resonance due to the parasitic capacitance components of the capacitors and diodes and the output inductor.
Can the voltage of a resonance waveform during discontinuous operation of a diode-rectifying DC/DC converter ever be greater than the input voltage?
The maximum value of the resonance waveform voltage is Vin + the Vf of the high-side MOSFET.
When a diode rectifying DC/DC converter is used in discontinuous operation, could there be an adverse effect on the IC or the peripheral components? What measures could I take if there were such an effect?
In the case of discontinuous operation, when there is a change in the load current such that operation changes from discontinuous to continuous, the transient response is slower, so that the output voltage change is somewhat larger. As measures to address this, there are such methods as increasing the capacitance of the output capacitor or increasing the inductance of the output inductor to set a ripple current that does not result in discontinuous operation.
Through-currents, dead time
What does it mean that there are "no through-currents" in diode rectifying step-down conversion as opposed to synchronous rectification?
In contrast with synchronous rectification, when using diode rectification the high-side transistor and the low-side transistor are never turned on simultaneously during operation. Therefore a short-circuit from Vin to GND due switching does not occur, and so the expression "no through-currents" is used.
Why is it that the through-currents that can occur in a synchronous rectifying DC/DC converter do not happen in a diode-rectifying DC/DC converter?
Due to the principle of operation under diode rectification, the switching transistors and diodes can never be turned on simultaneously, so through-currents do not occur.
What kind of phenomenon is a through-current?
In a synchronous rectifying DC/DC converter, when the high side transistor and the low side transistor are in the on state simultaneously, a short-circuit occurs between the high side input power supply (Vin) and the low side GND.
What is a through-current?
When the high side and low side transistors in a synchronous rectifying DC/DC converter are simultaneously in the on state, the high side input power supply (Vin) and low side GND are in a short-circuited (through) state, and the large current that flows is called a through-current.
I understand that in a synchronous rectifying DC/DC converter IC, the dead time is set so that a through-current does not flow. Are there ICs for which the dead time can be adjusted?
In nearly all synchronous rectifying ICs, the dead time is set so as to prevent through-currents; ICs that enable dead time adjustment are not ROHM products.
About what value is the dead time needed in a synchronous rectifying DC/DC converter?
In setting the dead time length, there is a trade-off: if set too long, the risk of a through-current is reduced, but efficiency is lower. In ROHM ICs, the dead time set in each model is optimized according to differences in the switching rise and fall times for the model. In the case of controller ICs with external switching transistors, the switching rise/fall times must be adjusted so that through-currents do not occur over the entire range of operating conditions.
How much conduction is allowed in the parasitic diode of a switching MOSFET of a synchronous rectifying DC/DC converter?
Because this differs among IC models, separate inquiries should be made.
In synchronous rectification, is it the case that for the low side MOSFET to turn on, first the parasitic diode (body diode) conducts, and then the MOSFET turns on?
The parasitic diode is always a diode structure that occurs when the MOSFET is in the off state. Therefore, the parasitic diode conducts while the low side MOSFET is turned off, and thereafter the MOSFET turns on.
Is a through-current not allowed in a synchronous rectifying circuit? For example, the time during which the through-current flows has to be short, or the through-current must be within the transistor ratings, etc.
Basically, the occurrence of a through-current is undesirable, and the IC deals with this by providing a dead time during which both transistors are turned off. Regarding the hypothetical conditions, operation may be possible, but considering efficiency and reliability, the through-current should probably not be allowed.
Light loading mode/pulse-skipping
Are the conditions for switching to light loading mode different depending on the component?
In essence, they differ depending on the external output inductor and the switching frequency of the power supply IC.
I understand that in light loading mode, efficiency is high even under a light load. I'd like to know why that is the case, and the conditions for switching to light loading mode.
During light loading, switching can be skipped (switching is made sparse) to improve efficiency. When the load current is roughly 1/2 or less of the inductor ripple current IL, skipping action is begun.
What happens to the switching frequency in pulse-skipping action during light loading of a synchronous rectifying DC/DC converter?
It depends on the load current. In the waveform of the inductor current IL during light loading, the area of the triangle shape corresponds to the electric charge accumulated in the output capacitor. When this charge is discharged by the load, the next switching cycle is performed. This interval determines the switching frequency.
What should I regard as the criteria for light loading and heavy loading in a synchronous rectifying DC/DC converter IC with a light loading mode?
Essentially, light loading means a discontinuous operation state, while heavy loading means a load for which a continuous operation state results. Switching between light loading operation and heavy loading operation differs with the IC and the external component values.
"Heavy loading" means about what percent of the output current rating?
In essence, heavy loading refers to a state of continuous operation; light loading is a state of discontinuous operation. In synchronous rectifying DC/DC converters with a light loading mode, switching between light and heavy loading differs with the IC and the external component values.
During pulse skipping in a synchronous rectifying DC/DC converter, how is an inductor current IL of zero detected?
There are a number of methods, but in general, it is detected using the low side MOSFET drain-source voltage.
How is the inductor current IL monitored during pulse skipping in a synchronous rectifying DC/DC converter?
There are a number of methods, but in general, it is detected using the lower MOSFET drain-source voltage.
A ringing-like vibration occurs in the switching waveform of a synchronous rectifying DC/DC converter during pulse skipping action. Could this adversely affect something else?
Resonance is not thought to have any effects in particular. Ringing is itself a sine wave-type phenomenon, and there are no higher harmonic components appearing as noise.
Is it the case that pulse skipping under light loading is a widely used feature in synchronous rectification-type ICs, which recently has frequently been included by all manufacturers in power supply ICs, or is it the case that this is patented technology and that power supply ICs with pulse skipping (and manufacturers) are limited?
Pulse skipping is a widely used technology.
I would like to know about circuits that, during pulse skip action under light loading of a synchronous rectification type device, detect that the inductor current IL has gone to zero.
Because this is an internal circuit of ICs, it cannot be made public.
In discontinuous operation of a synchronic rectifying DC/DC converter, does noise ever become greater than during continuous operation?
Because during discontinuous operation there is operation at a resonance frequency different from the stationary switching frequency, noise occurs in a low-frequency band distinct from the switching frequency.
Load, load transient response
Is there anything to be aware of when the load is not resistive, but is instead an inductor or a capacitor?
When an inductor (inductance) is the load, there are cases in which the backward current due to an emf must be taken into consideration.
What kinds of things are taken into consideration in the internal circuitry of a DC/DC converter IC to improve the load transient response characteristics of the IC?
Extension of the frequency characteristic of the feedback circuit to higher frequencies helps to improve the load transient response performance.
What kind of behavior does the output voltage exhibit when the load of a DC/DC converter changes suddenly?
When the load increases suddenly, the output voltage may drop temporarily; when the load decreases suddenly, it may rise temporarily. This load transient response characteristic depends on the frequency characteristics that are based on the IC and an adjustment circuit.
In the case of a DC/DC converter IC that automatically changes the switching frequency according to the load, in some cases overshoot when responding to a change from heavy loading to light loading can be large. Is there any means of dealing with this?
In general, to handle overshoot when there is a change from heavy to light loading, the output capacitance is increased.
I'd like to know about methods of protection from short-circuits during overloading.
While there are some differences depending on the IC, in general overcurrent protection, when a current has flowed that is greater than a limit value that has been set either within the IC or externally, the switching on duty is limited and the output voltage is lowered. When the output voltage has dropped to a certain value or lower, short-circuit protection is also activated to turn off output power transistors.
Is it possible to cause the overcurrent protection function to be activated at a desired current?
An IC should be selected that enables setting of the overcurrent detection value using an external resistor or the like.
Are ICs provided with protection circuitry?
While there are some differences depending on the type of IC and the protection function, protection functions are themselves provided within ICs. For ICs having variable protection function threshold values, the value is adjusted using an external component.
When designing a DC/DC converter, should the device be designed so as to result in continuous operation?
When the load current changes so as to include both continuous and discontinuous operation, the transient response characteristic is worsened somewhat compared with normal operation, and there is the possibility of large changes in the output voltage. Whether the load device can allow such changes becomes one guideline for design. If such changes cannot be allowed, either the problem is handled by adjustment of phase compensation component values for the IC, or in the design stage the addition of a dummy load is considered so as to prevent discontinuous operation. For standard load current value, in general a design is used that results in continuous operation.
Under what kind of conditions in discontinuous operation does the output current become greater than 1/2 of the ripple current?
When for example the ripple current is 400 mA, this happens when a load current of greater than 1/2 that, or 200 mA, is passed.
Does discontinuous operation have disadvantages, such as generating greater noise compared with continuous operation?
Because discontinuous operation is accompanied by a resonance frequency that is different from the basic switching frequency, noise occurs in a low-frequency band that is distinct from the switching frequency.
Maximum duty cycle (MaxDuty)
Output voltage setting range
In a synchronous rectifying DC/DC converter with a high/low-side Nch MOSFET configuration, what is the relationship between the maximum duty cycle MaxDuty and the output voltage?
The upper limit of the output voltage is limited by MaxDuty; the output voltage can be found using the following equation.
Vo: output voltage, Vin: input voltage, Io: output current, Ron: high side MOSFET on resistance, DCR: inductor series resistance
Why is it that, when the difference between the input voltage and the output voltage is large, the voltage is stepped down by passing through multiple DC/DC converters, for example in two stages?
ICs have a limited minimum on time, and the lowest step-down voltage is limited by this. In particular, when the switching frequency is high, the minimum on time occupies a larger fraction of the period, and a desired step-down voltage cannot be obtained. To deal with such situations, there is the method of using for example two stages to step down the voltage.
Minimum on time Ton(min)
Is the MaxDuty of a synchronous rectifying DC/DC converter affected by the minimum on time Ton(min)?
Yes, it is affected.
How is the minimum on time Ton(min), which limits the lowest output voltage of a synchronous rectifying DC/DC converter, determined?
Ton(min) is determined by the IC.
Maximum duty cycle (MaxDuty)
What determines the specification for the maximum duty cycle MaxDuty of a synchronous rectifying DC/DC converter configured with Nch MOSFETs as both the high side and low side transistors?
The internal circuitry of the IC.
Why is it that in a synchronous rectifying DC/DC converter with a high/low-side Nch MOSFET configuration, MaxDuty is limited and cannot be 100%?
The high side Nch MOSFET requires a bootstrap circuit for on operation, and in order to charge the step-up capacitor of this circuit with electric charge, the low side MOSFET must always be on with the switching pin in the "L" state. Because this interval (time period) is necessary, a limit on MaxDuty occurs, and it can never be 100%.
Does the value of the capacitor in the bootstrap circuit of a synchronous rectifying DC/DC converter with a high/low-side Nch MOSFET configuration affect MaxDuty?
In general, MaxDuty does not include parameters of the bootstrap capacitor, but if the capacitance value is too large, there may be an influence. The value recommended on the data sheet should be used for the capacitor of the bootstrap circuit.
A DC/DC converter IC that I am looking into has an input voltage of 7 to 35 V and an output of 0.8 V to Vin. Can it be used under the condition of a large difference in input and output voltages, with a 35 V input and 0.8 V output?
It is possible to calculate whether this is possible from the IC spec for the minimum on time. For example, if the minimum on time is 250 ns, then the minimum on duty ratio for a switching frequency of 100 kHz is 250 ns/(1/100 kHz)×100 = 2.5%. The minimum output voltage for an input voltage of 35 V is 35 V×2.5% = 0.875 V. If the IC is of the type that enables switching frequency selection, this can be dealt with by lowering the switching frequency. However, the values of the inductor and output capacitor will be larger.
I would like to estimate the amounts of heat generated by the different components for use in thermal design. What kinds of methods are there--manual calculations, simulations, something else?
Please explain the principle of voltage step-up in a DC/DC converter.
Similarly to step-down, energy is accumulated in an inductor, and the voltage is converted in on/off operation; but the circuit configuration is different. When the low side switching transistor is on, energy is stored in the inductor. When it turns off, the input power supply energy and the energy stored in the inductor are supplied to the output. By repeating this operation, a higher voltage than the input voltage can be generated.
Which current does the symbol Icc represent?
Normally, it is the circuit current of the power supply IC itself.
I think that, in comparison with LDOs, one disadvantage of DC/DC converters is their high cost. Is this correct?
DC/DC converters require a greater number of external components, so in terms of cost, they are at a disadvantage relative to LDOs.
How should I determine the reference voltage of the error amplifier that feeds back the output voltage of a power supply IC?
The reference voltage is the lowest voltage that can be output by a power supply IC. Hence for the power supply IC, the reference voltage should be set as low as possible. However, the lower the voltage is set, the lower will be the precision and noise immunity, and so at present standard practice is to set the reference voltage to approximately 0.7 V to 1.0 V.
What should I be aware of when choosing an LDO or a DC/DC converter as a power supply for a motor driver, considering sudden load changes such as when the motor is started?
Where motor applications are concerned, in many cases there are concerns about back emfs in particular; if a back emf exceeds the rated voltage for the power supply IC, the latter could be destroyed. Hence back emfs must be taken into account when choosing a power supply IC with an adequate voltage margin.