I am performing circuit simulations. When I apply a SiC MOSFET model to a circuit for which a Si MOSFET SPICE model operates normally, a "Time Step Too Small" error is returned and the simulation stops. Why is this?
The "Time Step Too Small" error occurs because calculations do not converge. One method that is known to improve convergence, is to use a resistance of about 1 MΩ to ground electrically floating nodes. Try DS and DG extrapolations.
In circuit simulations, a "Time Step Too Small" error is returned and the simulation stops. Connecting a resistance to each node doesn't help.
There is the possibility that in the simulation conditions, a maximum time step is not set. SiC device models use numerous exponential functions internally, and if time steps are coarse, convergence may be worsened.
The gate resistance value defined in the SPICE model for a SiC MOSFET differs from the data sheet value. Which is correct?
SPICE models for ROHM SiC devices are fitted to the characteristics of actual devices using various functions, and are configured using voltage control current sources and the like to reproduce the characteristics. The models for MOSFETs incorporated into simulators are not used.
Hence the defined gate resistances are different from the actual values. The data sheet values should be regarded as close to the actual values.
When a SiC device SPICE mode is read in, a syntax error occurs. What should I do?
Depending on the simulator, hyperbolic functions or inverse functions of these may not be interpreted.
Within the model there is a ".FUNC" list; if, before this list, lines to redefine TANH and ASINH are added, there may be no more errors.
However, if ASINH is replaced with a logarithmic function, care should be taken to ensure that a natural logarithm is not confused with a common logarithm.
For the natural logarithm notation, please refer to the simulator manual.
Is there any decline in the insulation resistance value when the upper part of the product molding is restrained by a metal spring?
Exposed metal parts (heat-dissipating parts on the package rear face, as well as exposed metal in cutouts) are at the same potential as the drain.
Hence when a metal plate is pressed against the surface of the package (the face on which markings are printed), there is the possibility that the creepage distance may be inadequate.
Customers should confirm creepage distance regulations in accordance with the environment of use.
What happens when the gate voltage of a second-generation planar SiC MOSFET product deviates from the recommended values (+18 V to +22 V when on, -3 V to -6 V when off)?
If, while the device is turned on, the gate voltage falls below 15 V, the device can no longer be kept adequately turned on, and below 14 V, the temperature characteristic of the on-resistance changes from positive to negative.
When this happens, if the temperature rises, the on-resistance falls, and there is the danger of thermal runaway. Hence care should be taken to always apply 15 V or more.
TZDB occurs at 40 V or higher, so there are no concerns about gate failure, but if a DC voltage exceeding the rating (-6 V/22 V) is applied continuously, the threshold value changes gradually due to the influence of traps existing near the gate oxide layer.
If the voltage is an instantaneous surge voltage (within 300 n sec), there is little influence to change the threshold voltage, and so voltages in the range -10 V to +26 V can be tolerated.
The diode specifications given in the spec sheets of SiC MOSFET products with internal SiC SBDs are the figures for which device--the body diode or the SiC SBD?
Because devices are connected internally, the characteristics cannot be distinguished from the outside.
However, because a SiC SBD has a low VF, in the normal operating range, a forward current flows only in the SiC SBD. Hence the If-Vf characteristic and the reverse recovery characteristic are in essence the characteristics of the SiC SBD.
Are there temperature conditions for the breakdown voltage specifications of SiC MOSFET products?
The condition is normal temperature (Ta = 25°C).
At high temperatures, there is a slight increase in the leak current and breakdown voltage.
About how great is the avalanche resistance of SiC MOSFET products?
We have not made all relevant measurements, and therefore at present cannot guarantee avalanche resistance. However, for a 1200 V, 80 mΩ product, the value is approximately 1.2 J.
I want to mount a discrete package on a heat sink; are there recommended screws and a specified torque?
There are no screws that are recommended in particular for a discrete package, but countersunk screws result in abnormal stresses and should not be used.
The tightening torque is from 49 Nm to 68.6 Nm.
When using self tap screws, please ensure that the torque upper limit is not exceeded. Screws should be tightened before soldering pins.
Is metal on the rear face of a discrete package insulated from other pins?
Exposed metal parts on the rear face are connected to the drain for MOSFETs, and are connected to the cathode for SBDs. Please use appropriate ground and other insulation.
What should I keep in mind about SiC-MOSFET parallel connections?
・If power wiring and the like is not made homogeneous, there may be imbalances in currents and chip temperatures.・If the timing of switching is not coordinated, overcurrents causing failure may occur.・If Vgs(on) is not sufficiently high, the Ron temperature characteristic is negative, current may be concentrated in a specific chip, and there is the danger of thermal runaway and failure
What is important to remember about SiC-MOSFET series connections?
・The upper device ground insulation can only be warranted to the insulation breakdown voltage of the device.・A floating power supply for the gate voltages of series devices is necessary.・For series-connected devices, the temperature coefficient of the on-resistance is positive, and so to prevent thermal runaway, sufficient current derating should be considered given variation among products.・When series-connected devices are used as a single switch with a high voltage, it is recommended that a high resistor be inserted in parallel or other measures taken to enable appropriate voltage division.・If the switching timing is not coordinated, breakdown voltage failure may occur.
What is the optimum external gate resistance value when connecting SiC MOSFETs in parallel?
If the gate signal wiring lengths are uniform, then the optimum value is about 1 to 3Ω. Resistors should be connected to each of the MOSFETs and the timing of the gate signals should be aligned.
If the wiring lengths are markedly different, a somewhat larger resistance value (about 10Ω) can be inserted to align the switching timing.
Why is there overshoot and undershoot of gate signals when driving a SiC product?
One possible cause is LC resonance, due to the effects of parasitic capacitance and parasitic inductance of the board. Please check the following:
① External gate resistors added to the gate drive circuit
② Output capacitance of the gate drive circuit
③ Parasitic inductance of gate drive circuit wiring
④ Gate capacitance of SiC MOSFETs
⑤ Internal gate resistance of SiC MOSFETs
If any resistances are too small, the overshoot/undershoot peak value will be large, and moreover time is required for ringing attenuation.
Also, a large capacitance means a smaller peak value, but the switching speed is slower.
If an inductance is large, the peak value is increased.
Please explain how to suppress gate signal overshoot and undershoot when using SiC products.
LC resonances may occur due to the parasitic capacitance and parasitic inductance of the board, and so the following should be checked:
① Use a large external gate resistance with the gate drive circuit.
② Decrease the output capacitance of the gate drive circuit.
③ Decrease the parasitic inductance of wiring in the gate drive circuit.
If resistances are small, overshoot/undershoot peak values are higher, and time is required for ringing attenuation. If capacitances are large, switching speeds are lower. Inductances should be made as small as possible.
Is a negative bias necessary for the gate voltages of SiC MOSFET and SiC module products?
When the drain potential rises with the FET in the off state, due to an AC coupling phenomena of the gate-drain capacitance, there is the possibility that the gate potential may be pulled upwards. A representative application is series-connected bridge driving.
In order to prevent short-circuit failures caused by erroneous device turn-on, it is recommended that a negative bias be used.
Pulling-up of the gate potential can also be suppressed by adding capacitance across the gate and source.
In addition, by connecting a mirror clamp MOSFET across the gate and source for reliable short-circuit, gate potential pulling-up can be prevented.
Care should be taken to prevent erroneous operation of the mirror clamp MOSFET due to noise.
Is there a recommended inductance value of the gate drive circuit for SiC MOSFET and SiC module products that is allowable for gate signals?
We do not provide specific guidelines.
The most important factor is the length of the wiring from the device gate pin to the bypass capacitor pin of the gate drive circuit. The inductance of wiring from the device source pin to the ground pattern on the board must also be considered.
Why is the internal gate resistance of a SiC MOSFET high compared with that of a Si MOSFET?
Rg is inversely proportional to the chip size, and so Rg will be higher for a SiC device with a smaller chip size.
In addition, the material of the gate electrode has a high sheet resistance.
No problems should arise even if the external gate resistance of the gate drive circuit is 0Ω, but the driver current capacity, surges and the like should be considered.
Why is the recovery current of a SiC MOSFET body diode so much smaller than that of a Si MOSFET?
While the body diode of a SiC MOSFET is a PN junction, because the minority carrier lifetime is short, there is almost no accumulation effect of minority carriers, and so recovery performance is ultra-fast (on the order of tens of nanoseconds), comparable to SBDs.
Why is the recovery time of a SiC MOSFET body diode much shorter than that for a Si MOSFET?
The body diode of a SiC MOSFET is a PN junction, but the minority carrier lifetime is short, and minority carriers have almost no accumulation effect, and so the recovery performance is ultra-fast (on the order of tens of nanoseconds), comparable to SBDs, and like SBDs the recovery time is constant and independent of the forward injection current (when dI/dt is constant).
Why is the forward voltage drop of the body diode of a SiC MOSFET so high?
Because the band gap of SiC is about three times that of Si, the threshold voltage of a PN diode is high at about 3 V, and the forward voltage drop is comparatively high.
The minority carrier lifetime is short and there is almost no accumulation effect, and therefore it is thought that the diode on-resistance is not lowered.
However, in a bridge circuit or other applications, if a gate-on signal enters during switching, reverse current conduction is possible, and so steady-state losses are in effect not much of a problem.
Regarding SiC MOSFET device structures, what are the advantages and disadvantages of planar and trench type structures?
The advantages of trench type devices include:
① Low on-resistance
② Small parasitic capacitance
③ Good switching performance
One disadvantage is a small short-circuit capacity due to the low on-resistance.
How do I calculate switching losses?
Based on the drain-source voltage and the lower limit of the drain current, the product of the two is integrated over the following interval.
During turn-on: (start) point at which the drain current begins to rise; (end) point at which falling of the drain-source voltage ends
During turn-off: (start) point at which the drain-source voltage begins to rise; (end) point at which the drain current falling ends
SiC SBD data sheets do not give reverse recovery loss values Err; how should this value be estimated?
Because there is no carrier accumulation in SBDs, there is no reverse recovery phenomenon.
However, parasitic capacitance is present, and switching losses occur due to the associated charging and discharging.
For example, when a SCS240AE2C is operated at 250 kHz and 400 V, a rough calculation gives:
fQV = 250 kHz x (31nC x 2) x 400 V = 6.2 W
The current is unrelated.
A graph of the current dependence of the reverse recovery time is not provided on SiC SBD data sheets. How should this be estimated?
The "switching time (tc)" in the table is the reverse recovery time. In the case of an SBD, the reverse recovery time does not depend much on the current or temperature, and so graphs are not provided on data sheets.
What are the parasitic reactances of the gate, drain and source set in SPICE models for SiC module products?
These are values that conform to actual characteristics, and are not derived from structural elements. They should be regarded as reference values.
Source: L = 1.75ｎH and R = 1Ω in parallel
When SiC module products are stored, is it necessary to short-circuit the device pins?
Short-circuiting is recommended.
However, if the product is in a state in which passing of currents and static buildup are prevented, short-circuiting is not necessary.
I want to fasten a gate drive board to a SiC power module. Are there recommended screws and a specified torque?
Screws recommended for board mounting are B-TITE or P-TITE self-tap screws, which are well-suited for use with plastics, with a nominal diameter of 2.6 mm and pitch of 0.9 mm.
The tightening torque should be approximately 60 to 80 cNm.
Screws should be tightened before soldering gate pins etc.
Is it better to short-circuit and connect the output pins  and  of a power module?
Can the rated current be output from one of the pins even if there is no external short-circuiting?
Either of pins 3 and 4 can output the rated current independently.
However, the upper-arm and lower-arm inductances are not completely symmetric, and so when considering balance it may be better to use wiring that connects the pins. The wiring resistance is also lowered.
Is metal on the rear face of a power module insulated from other pins?
Metal on the rear face and mounting hole collars are insulated from other pins. Insulation breakdown voltages are listed on data sheets.
Are there any tools for evaluating SiC module products?
We can provide the following tools.
・Gate drive circuit reference board (BW9499H/BP59A8H)
・Snubber capacitor module (EVSM1D72J2-145MH16/26)
Are wiring inductances and parasitic capacitances included in a SPICE model of a SiC product?
Models are generated on the basis of the results of characteristic measurement, and so in essence, they are included. However, even if equivalent components were defined, they would not reflect actual parasitic components.
What are operating environments for SPICE models of SiC products?
The following have been confirmed as operating environments for the "PSpice” version software:
Because the "HSpice" version does not support hyperbolic functions, models may not operate properly.
What are the grades of SPICE models for SiC products?
"Behaviour model" only.
Function groups based on the operating principles of silicon-based devices cannot be used for SiC devices.
Are there any plans to release any SiC products with rated voltages other than 650 V, 1200 V or 1700 V (such as 300 V, 900 V, etc.)?
At present there are no such plans.
Why is it that drain-source rated currents are different for discrete SiC products and for SiC module products?
This is because usage temperature conditions are different.
Modules: Junction temperature (Tj) 150°C, case temperature (Tc) 60°C
MOSFETs: Junction temperature (Tj) 175°C, case temperature (Tc) 25°C
It is said that SiC devices can operate at high temperatures. Why is it that ROHM SiC products have Tj values of up to 175°C?
The value is limited by the thermal resistance of the sealing resin material used in the package, the solder, and other metal bonding materials.
Moreover, due to problems with the reliability of bonding with SiC devices, the upper-end temperatures of thermal cycle tests and power cycle tests cannot be raised.
Are there a recommended circuit configuration and circuit constants for a gate drive circuit for a SiC MOSFET or module product?
There is a gate drive circuit reference board. (This is a driving board that assumes direct mounting on a SiC module product.)
When SiC MOSFETs are connected in parallel, external gate resistors should be connected to each of the MOSFETs to balance the gate signals.