2021.08.18

Points of this article

・When the gate resistance of a switching element is increased, noise is suppressed, but there is a tradeoff with reduced efficiency. Hence it is extremely important that the gate resistance be set so as to achieve a balance.

・Simulations can be used to determine the maximum value of the gate resistance R_{G} when holding switching element losses to below a specific value.

In actual circuit design, noise reduction is a major issue, and in general noise is suppressed when the gate resistance of a switching element is increased. However, because there is a tradeoff due to the fact that efficiency is reduced (losses increase), it is extremely important that the gate resistance be set so as to balance the two. Here, the maximum gate resistance R_{G} when switching element losses are held below a prescribed value is studied. To study noise, evaluations using actual equipment are necessary, and so here noise issues are not addressed.

As an example circuit, the simulation circuit “A-5. PFC CCM 2-PhaseVin=200V Iin=5A” in the Power Device Solution Circuit/AC-DC PFC list is used (see Fig.13). Details of the circuit diagram can also be seen here.

In this example, while holding losses in the SCT2450KE SiC MOSFET that is the low-side switching element in Fig. 13 to 5 W or less, we use simulations to study how high the gate resistance R_{G} can be set in order to deal with noise.

Fig. 13: PFC simulation circuit “A-5. PFC CCM 2-Phase V_{in}=200V I_{in}=5A”

Fig. 14 shows the relationship between losses, the drain current I_{D}, the drain-source voltage V_{DS}, and the gate voltage V_{GS} when the SiC MOSFET is turned on. The periods t1 and t2 during which the switching loss occurs can be represented as follows.

From these equations, we see that the times t1 and t2 at which switching losses occur are proportional to R_{G}. Moreover, at these times I_{D} and V_{DS} change approximately linearly, and so losses can also be considered to be proportional to R_{G}.

Fig. 14: Relation between losses, I_{D}, V_{DS}, and V_{GS} when turned on

Fig. 15 shows the results of simulation of SiC MOSFET losses when R_{G} is changed. To avoid complexity, the resistance values for the source and the sink are changed in equal multiples.

Fig. 15: SiC MOSFET loss simulation results when R_{G} is changed

These simulation results show that, while the conduction loss is constant and unaffected by R_{G}, the switching loss, as explained in “The Relationship Between Gate Resistance and Losses” above, is proportional to the value of R_{G}. In order to hold losses to under 5 W, we see that R_{G} must be held to within 9 times the initial value; that is, resistance values should be set such that R_{G(SOURCE)} is 45 Ω or less, and R_{G(SINK)} is 18 Ω or less.

Downloadable materials, including lecture materials from ROHM-sponsored seminars and a selection guide for DC-DC converters, are now available.