About Surges in Gate-Source Voltages

Power semiconductors such as MOSFETs and IGBTs are used as switching elements in various power supply applications and power lines. Among these devices, SiC MOSFETs have been used more and more frequently in recent years, and operate so rapidly that the effects of the inductance of the package of the MOSFET itself and the wire self inductance of peripheral circuits on changes in voltage and current during switching cannot be ignored. In particular, when the voltage or current of the device itself changes, unexpected surges may occur in the gate-source voltage, necessitating special measures. Here we examine and consider such measures. Surges occurring in gate-source voltages are explained in detail in “SiC MOSFETs: Behavior of Gate-Source Voltage in a Bridge Configuration” in the Applications Edition of the Tech Web Basic Knowledge section on SiC Power Devices, which the reader is invited to consult.

About Surges Occurring in Gate-Source Voltages

The circuit diagram on the right is the simplest synchronous boost circuit that uses MOSFETs in a bridge configuration. In this circuit, the high side (hereafter HS) SiC MOSFET is switched in synchronization with switching of the low side (LS) SiC MOSFET. When the LS turns on, the HS turns off, and when the LS turns off the HS turns on, in alternating on/off operation.

Through this switching, surges occur not only on the switching LS, but also on the synchronized HS according to changes in the voltage and current on the switching LS.

The waveform diagram below shows the waveforms of the drain-source voltage (V_DS) and the drain current (I_D) upon LS turn-on and turn-off in the circuit, as well as the behavior of the gate-source voltage (V_GS). The horizontal axis represents time, and time intervals Tk (k = 1-8) are defined as follows.

 T1: Interval during which LS is on and the SiC MOSFET currents are changing
 T2: Interval during which LS is on and the SiC MOSFET voltages are changing
 T3: Interval during which LS is on
 T4: Interval during which LS is off and the SiC MOSFET voltages are changing
 T5: Interval during which LS is off and the SiC MOSFET currents are changing
 T4 to T6: Dead time interval until HS turns on
 T7: Interval during which HS is on (synchronous rectification interval)
 T8: Dead time interval from turn-off of HS to turn-on of LS

Phenomena (I) to (VI) indicated by arrows occur in the gate-source voltage V_GS. The broken lines represent the original waveforms without surges. These phenomena occur for the following reasons.

 Phenomena (I), (VI) → Change in drain current (dI_D/dt)
 Phenomena (II), (IV) → Change in drain-source voltage (dV_DS/dt）
 Phenomena (III), (V) → End of change in drain-source voltage

Among these phenomena, the gate-source voltage surges that we will examine here are the phenomenon (II) occurring on the HS upon LS turn-on, and the phenomenon (IV) occurring on the HS upon LS turn-off, which particularly affect device operation.