Positive Voltage Surge Countermeasures

In the previous article, examples of circuits to suppress surges occurring in the gate-source voltage were presented. Here, examples of positive surge countermeasures and their effects are described.

Surges occurring in gate-source voltages have already been explained in detail in the previously mentioned “SiC MOSFETs: Behavior of Gate-Source Voltage in a Bridge Configuration” in the Applications Edition of the Tech Web Basic Knowledge section on SiC Power Devices, and should be referenced as necessary.

Positive Voltage Surge Countermeasures

The diagram on the right shows the gate-source voltage behavior when LS is turned on in the synchronous boost circuit presented previously. In order to suppress a positive surge in the HS (non-switching side) V_GS (phenomena II), as indicated in the table in the previous article, a mirror-clamping MOSFET Q2 in the surge suppression circuit, or a false turn-on suppression capacitor C1, are effective (see the test circuit described below).

In order to test the effect of a suppression circuit, the suppression circuit was installed separately on an SiC MOSFET (SCT3040KR) driving circuit, and waveforms were observed. For reference, the outer appearance and main specifications of the SiC MOSFETs are shown below.

The circuits below are suppression circuits to be tested. There are four circuit types: (a) is the circuit without the suppression circuit, (b) includes only a mirror clamp MOSFET (Q2), (c) includes only Schottky barrier diodes D2, D3, C2 for clamping, and (d) has only a capacitor C1 for false turn-on suppression. The V_GS surge voltage was determined by double-pulse tests.

Double-pulse test waveforms obtained using the test circuits are shown. Those below are the waveforms during turn-on; from the top, they are the switching-side gate-source voltage (V_{GS_HS}), the non-switching-side gate-source voltage (V_{GS_LS}), the drain-source voltage (V_DS), and the drain current (I_D). Four sets of waveforms are displayed superposed; these are for the above suppression circuits (a), (b), and (c), and also, as waveform (e), the waveforms of the positive voltage suppression circuit (b) presented in the previous article. The circuit for (e) is provided with all the suppression circuits in (b) through (d) above.

As is clear from the above waveforms, the positive surge voltage could not be subdued in circuit (a), which did not have a countermeasure circuit, or in (c), which had only SBDs for clamping, and the rise in V_{GS_LS} is apparent; it is seen that the gate turn-on threshold voltage is greatly exceeded, and I_D is also far greater than in the other circuits. In other words, false turn-on of the MOSFET on the non-switching side (in this case, LS) occurred.

In order to prevent this erroneous operation, countermeasure circuit (b) provided with a mirror clamp circuit is essential. In order to implement the mirror clamp circuit, a control signal that drives the mirror clamp MOSFET is needed. This signal must control the driving timing while monitoring the voltage V_GS, and because many driver ICs are generally provided with such a function, if using a driver IC that is not equipped with such a control function, implementing a countermeasure circuit becomes difficult.

In such a case, as indicated in the test circuit (d), a false turn-on suppression capacitor C1 can be connected between the MOSFET gate and source to serve as a surge countermeasure circuit. Below are shown turn-on waveforms when such a false turn-on suppression capacitor C1 is connected. Waveform (a) is for when C1 is not present, and waveforms (b), (c), and (d) are for C1 values of 2.2 nF, 3.3 nF, and 4.7 nF. Compared with case (a) in which there is no capacitor C1, we see that the swelling in V_{GS_LS} is diminished in (b), (c) and (d), and the I_D turn-on surge is also smaller.

However, as is also clear from the I_D waveforms, when a false turn-on suppression capacitor C1 is connected, the turn-on operation is delayed according to the capacitance of C1, and consequently the switching loss increases. Hence the capacitance of C1 must be set to the smallest value possible. Judging from these evaluations, it can be said that 2.2 nF, the value for waveform (b), is appropriate.

The next article will describe measures to deal with negative voltage surges.