Tips for Practical Use: Gate Driving–Part 1

From here, we examine how to make full use of the superior performance of full-SiC power modules. This time, we explain gate driving, and in Part 1 examine issues relating to gate driving, whereas in the following Part 2 we will discuss methods for coping with a problem explained here.

Issues Relating to Gate Driving: False Gate Turn-On

To begin with, it must be noted that from this point forward the matters to be studied are not specific to full-SiC power modules, but are instead problems that require study in the case of individual SiC MOSFETs as well. This information will also be of use in designs that use discrete components.

“False gate turn-on” is a phenomenon in a configuration using a high-side SiC MOSFET and a low-side SiC MOSFET in which, at the time of SiC MOSFET transition (switching), ringing occurs in the gate voltage of the high-side SiC MOSFET, or the gate voltage of the low-side SiC MOSFET is raised, causing the SiC MOSFET to operate erroneously. The essence of this phenomenon can be understood easily by referring to the following waveform diagram.

The green trace is the gate voltage of the high-side SiC MOSFET (VgsH), the red represents the low-side gate voltage (VgsL), and the blue is Vds. Ringing and oscillation are observed in all of these, making them waveforms that do not inspire optimism. If for example false turn-on occurs when the low side must be turned off, there is the possibility of problems such as a through-current flowing between the high side and the low side.

This phenomenon arises due to the extremely fast switching that is one feature of SiC MOSFETs. The rising of the low-side gate voltage occurs due to the ringing in Vd that occurs during the transition to high-side turn-on, and the parasitic capacitance of the gate of the low-side SiC MOSFET.

Switching Speed and Parasitic Capacitances in Full-SiC Power Modules

The characteristic switching speed and parasitic capacitances of a full-SiC power module, which are related to ringing and rising of gate voltages, are here compared with conventional IGBT power modules.

Switching Speeds: Comparison with IGBTs

The graphs below compare dV/dt, that is, switching speed when the switch is on and off for a full-SiC power module and an IGBT module. The dV/dt when the switch is on in the SiC module is about the same as for the IGBT module, depending on the external gate resistance Rg. When the switch is off, since the SiC module does not have a tail current unlike in the case of IGBTs, the dV/dt depends on the external gate resistance Rg, similarly to when the switch is turned on.

Parasitic Capacitance: Comparison with IGBTs

Parasitic capacitances in MOSFETs (or IGBTs) include Cgd (Cgc) between the gate and drain (or collector), Cgs (Cge) between the gate and source (or emitter), and Cds (Cce) between the drain (or collector) and the source (emitter). Of these, Cgd and Cgs are related to the rising of the low-side gate voltage.

The graph on the lower left shows the relationships of Cgd (Cgc) with Cgs (Cge) and Vds (Vce). Curves not labeled as applying to SiC modules are for IGBTs. As the curves indicate, the parasitic capacitances are roughly the same, and the characteristics are also similar. The graph on the right shows the ratio of Cgd (Cgc) to Cgs (Cge), which is called the parasitic gate capacitance ratio; it is a parameter that affects the rising of the low-side gate voltage. As can be inferred from the actual capacitance values in the graph on the left, the parasitic capacitances are about the same.

Mechanism of Gate Voltage Rising

As mentioned above, rising of the low-side SiC MOSFET gate voltage is due to the fast dV/dt when the high-side SiC MOSFET is switched on; an increase ΔVgs in the gate voltage occurs due to the parasitic gate capacitance and gate impedance of the low-side SiC MOSFET.

The switching-on speed of a SiC MOSFET depends on the external gate resistance Rg, as indicated in the graph above; if Rg is low, dV/dt becomes high.

The gate parasitic capacitance is essentially something that is present and cannot be adjusted, and so, given that the gate parasitic capacitance is present as a fixed quantity, and taking the low-side gate impedance to be a cause of ΔVgs, we consider the external gate resistance Rg, which can be adjusted.

This figure indicates the relationship of the low-side gate voltage rise ΔVgs to the high-side external gate resistance Rg_H and the low-side external gate resistance Rg_L. As can be seen from the graph, the smaller the high-side Rg_H, that is, the higher the value of dV/dt, and the larger the low-side external gate resistance, the higher the resulting ΔVgs.

Next time, we will examine methods for dealing with the rise in the gate voltage, drawing on the above considerations.