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• SiC MOSFETs Adopting 4-pin Packages：SCT3xxx xR Series : Switching Losses Slashed 35% Using Driver Source Pin

SiC MOSFETs Adopting 4-pin Packages: SCT3xxx xR Series

# Switching Losses Slashed 35% Using Driver Source Pin

## －Part 2－

Keyword MOSFET driving circuit with a driver source pinReturn line of driving circuitDouble pulse testSwitching loss comparative dataLoss reduced about 38%Smaller circuit scaleHigher power level for a given sizeReduced loss for improved efficiency and decreased heat dissipationMatters to be studied for 4-pin package devices

－Now I'd like to ask about how switching losses can be reduced using a driver source pin. First of all, could you please explain a circuit that uses a driver source pin and its operation?

Figure 4 is an example of a MOSFET driving circuit with a driver source pin. The only difference with Figure 2, which is a conventional driving circuit, is that the return line of the driving circuit is connected to the driver source pin. Please compare this figure with Figure 2, which we saw earlier.

As is clear from the circuit diagrams, LSOURCE is not included in the driving circuit system that includes VG, and so we see that the effect of VLSOURCE due to the change in ID during switching operation is completely absent.

The voltage VGS_INT applied internally to the chip is expressed by equation (2). Naturally, in this equation there is no term involving LSOURCE that depends on equation (1) for a 3-pin package. Hence VGS_INT for the MOSFET with the 4-pin package is affected only by the voltage drop VRG_EXT due to RG_EXT and IG, and because RG_EXT is an external resistor, it can be adjusted. For comparison we also include equation (1) below.

－Could you please show us some comparative data?

There is comparative data from double pulse tests. In order to compare the switching operation of SiC MOSFETs, one a conventional device and the other having a driver source pin, the circuit shown in Figure 5 was used to perform double pulse tests in which a low side (LS) MOSFET was switched. On the high side (HS) in this circuit, RG_EXT was connected to the source or the driver source pin, and the high side was used only in commutation operation by the body diode.

Figure 6 shows the waveforms of the drain-source voltage VDS and the drain current ID at turn-on. Driving conditions were RG_EXT = 10 Ω and VDS = 800 V, and the waveforms are for an ID of about 50 A.

The TO-247-4L package, represented by the red traces, has four pins, whereas the TO-247N, corresponding to the blue waveforms, is a conventional 3-pin package; the SiC MOSFET chips within these devices are the same.

To begin, please compare the ID waveforms, appearing as broken lines. Compared with the blue waveform for the 3-pin package, the red ID rising waveform for the 4-pin package is sharp, and the time required until 50 A is reached is, of course, short.

It appears that there is not such a great difference in the fall time of VDS, but switching from the time the gate signal is input is clearly faster.

－As you explained earlier, the only difference is that in a 4-pin package the effect of LSOURCE is eliminated by providing the driver source pin. So can we then conclude that the difference in switching characteristics is due only to the presence or absence of LSOURCE?

In essence, that is correct. Of course, there are factors that need to be examined closely, but when the influence of LSOURCE is eliminated from the gate driving circuit system, switching is faster, for the reason explained using Figure 4. Switching during turn-off, although not so prominent as during turn-on, is also faster.

－And as a result, switching losses are dramatically improved, aren't they?

This is comparative data for switching losses pertaining to both turn-on and turn-off.

The switching loss during turn-on, which had been 2,742 μJ, improved to 1,690 μJ, so that losses were reduced about 38%. During turn-off also, losses dropped from 2,039 μJ to 1,462 μJ, for a decrease of approx. 30%.

－I see. Could you please summarize all this then.

SiC MOSFETs combine the features of ultra-low on-resistance and fast switching, and make possible smaller circuit scales, higher power levels for a given size, and reduced losses for improved efficiency and decreased heat dissipation.

However, when it comes to mounting power devices in switching circuits that handle large amounts of power, the effects of parasitic components such as parasitic inductance must be considered, and as switching currents increase and switching becomes faster, these effects grow ever greater. This is an issue not only involving the board on which devices are mounted, but also the packages used for the devices.

This is the context for the adoption of the 4-pin package for the most recent generation of SiC MOSFETs. In applications that use SiC power devices, the aim was to achieve even lower losses.

One thing to be born in mind here is matters to be studied in order to effectively use 4-pin package devices. Here we have explained how, by removing the influence of the package inductance LSOURCE, the switching speed was improved and switching losses could be greatly alleviated. These are facts, but when considering stability and overall circuit operation, there are a number of matters that must be studied due to the faster switching speeds. As the word "trade-off" implies, there is always a need for optimization in terms of what takes priority in the circuit, using the greatest common divisor, so to speak.

There are plans to publish an explication of these matters in the "SiC Power Devices" corner for basic knowledge of the Tech Web. In addition, the Application Note on which the present discussion was based, Improvement of Switching Losses Through Driver Source Pins (PDF) can be downloaded from the website (*1).
*1：The English version is not available, as of May 14 2020.

－Thank you very much.

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