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SiC MOSFETs Adopting 4-pin Packages:SCT3xxx xR Series : Reasons for Adopting 4-pin Package


ROHM recently released the SCT3xxx xR series, a new series of SiC MOSFETs. The SCT3xxx xR series achieves still lower on-resistances through the adoption of a new trench gate structure, and at the same time improves switching characteristics by using a 4-pin package provided with a separate source pin for gate driving. As a result, switching losses can be cut by about 35%. We asked a ROHM application engineer about the reasons for adopting the 4-pin package, the effect of using this package, and related issues.

-About the SCT3xxx xR series of SiC MOSFETs, I was very interested to learn that in addition to the low on-resistance, a 4-pin package was adopted to enable a 35% cut in switching losses. Today, I’d like to focus my questions on this 4-pin package.

-To begin with, could you please explain what the 4-pin package is, and summarize the reasons and motives for its adoption?

First off, the 4-pin package was adopted with the objective of improving the switching losses of SiC MOSFETs. Not only SiC MOSFETs, but MOSFETs and IGBTs for power switching can also be used as switching elements in various power supply applications and power lines. The switching losses and conduction losses occurring in such switching elements must be reduced to the extent possible, and there are various approaches to lowering losses, depending on the application. As one such method, in recent years a 4-pin package has been announced that provides, in addition to the three pins for the source, drain, and gate of a MOSFET, a separate driver source pin. Here, by adopting a 4-pin package for the SCT3xxx xR series, in which a still lower on-resistance is achieved and conduction losses are reduced through use of the latest trench gate structure, the fast switching performance inherent in SiC can be exploited, and switching losses are further reduced as well.

-Well, I’d like to ask about the details of some of the aspects of this summary. First, what do you mean by a “driver source pin”?

A driver source pin is a source pin that uses the principle of a Kelvin connection. Kelvin connections are well-known in resistance measurements using four pins or four wires in which, in addition to a current path, two wires are provided for voltage measurement so as to eliminate to the extent possible the effects of cable resistance and contact resistance, which cannot be ignored when measuring minute resistances or making measurements using large currents. This 4-pin package uses a Kelvin connection only at the source: by providing a source voltage pin to connect a return wire to the gate driving circuit separately from the power source pin to pass large currents, the effect of ID on the gate driving circuit is eliminated.

-So the basic approach is to use a Kelvin connection.

That’s right. We will look at an actual package later, but first I’d like to explain why the driver source pin contributes to reducing switching losses.

MOSFETs are generally voltage-driven, and a MOSFET is turned on and off by controlling the voltage at the gate pin. Figure 1 shows an example of a general gate driving circuit for a conventional 3-pin package (TO-247N) MOSFET. The red dashed line indicates the boundary separating the MOSFET package interior and exterior.

Normally, an external gate resistor RG_EXT to control the switching speed is inserted between the driving power supply VG and the MOSFET gate pin, and the wiring inductance LTRACE of the printed circuit board is also included. In addition, a package inductance LSOURCE between the source pin and the MOSFET chip is also included.

Among the parasitic components, the package inductance of the gate pin is included in LTRACE, but the package inductance LDRAIN of the drain pin is not included in the gate driving circuit system, and so is here omitted.

-So this is about the basic gate resistance and parasitic components in MOSFET driving.

Yes. However, although this may not exert a large effect at the switching speeds of general IGBTs, under the conditions of the fast switching that is one feature of SiC MOSFETs, the switching-induced transitions of the drain-source current ID and the voltage VLSOURCE due to LSOURCE become problems.

This is explained in somewhat more detail in Figure 2, which shows how voltages behave in the circuit during switching operation.

When VG is applied and the MOSFET is turned on, ID increases suddenly, and an EMF VLSOURCE(I), shown in the figure, appears across LSOURCE.

Because the current IG flows into the gate pin, a voltage drop VRG_EXT(I) appears across RG_EXT.

The same mechanism gives rise to a voltage across the gate line LTRACE, but this is very low with little influence, and so is here omitted.

These voltages are included in the driving circuit network during turn-on, and so the voltage VGS_INT actually applied to the chip within to turn on the MOSFET is reduced. The reduction in VGS_INT can be expressed using equation (1).

-In other words, the VGS_INT that is actually applied to the inner chip is the voltage that results upon subtracting from the gate applied voltage VG the voltage drop due to the external gate resistor and the EMF due to the parasitic inductance of the source pin.

That’s right. When VGS_INT is reduced in this way, the speed with which the MOSFET turns on, that is, the switching speed, is reduced.

The situation is similar when turning off, and equation (1) can be applied. However, because IG and dID/dt are negative, voltage increases, indicated by (II) in the figure, occur across RG_EXT and LSOURCE, and conversely, VGS_INT increases. When this increases, this time the turn-off speed declines.

-So the switching speed falls because of RG_EXT and LSOURCE. But RG_EXT is the external gate resistor, so couldn’t its value be reduced to lessen the effect it has?

As you say, by reducing the value of RG_EXT, the switching speed is increased. RG_EXT is originally used to adjust the switching speed, and so it should be understood that if RG_EXT is made larger than necessary, the switching speed drops and switching losses increase.

However, LSOURCE is a parasitic component within the package, and so cannot be adjusted from outside. This is an extremely important point. In general, LSOURCE in a power switching device ranges from several nH to less than 20 nH, and when dID/dt reaches several A/ns, an EMF VLSOURCE of 10 V or higher may be generated, greatly affecting switching operation.

-I wasn’t sure about this when you gave us the equation, but it makes sense to me now.

As you would expect, in order to eliminate the effect of this VLSOURCE, the package construction must be modified. This is why we adopted the 4-pin package in which the power source and the source for the driver are separated.

Our introduction has been a bit long, but now let’s look at examples of 4-pin packages. At present, packages used in ROHM products are the TO-247-4L (a) and the TO-263-7L (b).

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