Semiconductor Memories｜Basic
Mask ROM ＜Semiconductor Device Principles＞
table of contents
Mask ROM Memory Cell Configuration
Adopts a NAND structure for increased integration (1 transistor cell).
Data Write Method
- Information written in the wafer process
- ‘1’ : Ions implanted in the transistor
- ‘0’ : No ion implantation
Data Read Method
- Word line potential of the Read Cell is 0V
- Word line potential of non-Read Cell is Vcc
- Voltage is supplied to the Bit Line
- ‘1’ is determined if current flows
Semiconductor Memories
Basic
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What is Semiconductor Memory?
- What is Semiconductor Memory?
- DRAM ＜Semiconductor Device Principles＞
- SRAM ＜Semiconductor Device Principles＞
- Mask ROM ＜Semiconductor Device Principles＞
- EEPROM ＜Semiconductor Device Principles＞
- Flash Memory ＜Semiconductor Device Principles＞
- Interface Selection
- Pin Layout and Functions
- Command Comparison
- Application Example: Configuring Multiple EEPROMs (I2C)
- Application Example: Configuring Multiple EEPROMs (SPI)
- Application Example: Configuring Multiple EEPROMs (Microwire)