SiC Power Device|Application

Negative Voltage Surge Countermeasures

2023.09.27

Points of this article

・Countermeasures to deal with negative surges in the gate-source voltage can prevent false HS turn-on while the LS is on.

・This is done by adding special circuits, shown in the example circuits.

・Surge suppression using a mirror clamp is difficult when the gate driver IC has no relevant control functions.

・As a replacement for a mirror clamp, in consideration of positive surges, a clamping Schottky barrier diode and a false turn-on suppressing capacitor can be used together for optimization.

In succession to the previous article on “Positive Voltage Surge Countermeasures“, this article presents examples of countermeasures to deal with negative voltage surges and the effects of these measures.

Surges occurring in gate-source voltages have already been explained in detail in the previously mentioned “SiC MOSFETs: Behavior of Gate-Source Voltage in a Bridge Configuration” in the Applications Edition of the Tech Web Basic Knowledge section on SiC Power Devices, and should be referenced as necessary.

Negative Voltage Surge Countermeasures

The diagram on the right shows the gate-source voltage behavior when LS is turned off in the synchronous boost circuit presented previously. In order to suppress an phenomena IV, which is a negative surge in VGS on the HS (non-switching side), it is effective to use either a MOSFET Q2 for mirror clamping or a clamping SBD (Schottky barrier diode) D3, as previously summarized in a table in the article on “Surge Suppression Circuits” (see the test circuit described below).

The circuit below is the same as the suppression circuit used in verification of positive surge countermeasures in the previous article. There are four variations: (a) has no suppression circuit, (b) has only a MOSFET (Q2) for mirror clamping, (c) has only Schottky barrier diodes for clamping, and (d) has only a false turn-on suppression capacitor C1. Using these circuits in double-pulse tests, VGS surge voltages were observed.

The following are waveforms at turn-off obtained from double-pulse tests. Shown from the top are the switching-side gate-source voltage (VGS_HS), non-switching-side gate-source voltage (VGS_LS), drain-source voltage (VDS), and drain current (ID). The four waveforms are displayed in superposition for the above suppression circuits (a), (b) and (c), as well as for a circuit (e) that combines all the suppression circuit components of (b) and (c).

From these waveform diagrams, we see that except for (a), which has no countermeasure circuit components, negative surges could be eliminated in all of the suppression circuits.

Next, the turn-off waveforms in double-pulse tests for the test circuit (d) with only the false turn-on suppression capacitor C1 connected are shown below. The circuit diagram is the same as that shown previously. Waveforms (a) are for comparison and are for the case without capacitor C1; the waveforms (b), (c) and (d) are for C1 values of 2.2 nF, 3.3 nF, and 4.7 nF. Compared with waveforms (a) without a capacitor C1, the negative surge in VGS_LS is somewhat reduced for (b), (c) and (d) with a capacitor C1 added, but the effect of the added capacitor is inadequate. Hence as a surge countermeasure, one among the suppression circuits (b) and (c) should be selected; but because (c) cannot suppress positive surges, the only remaining option is (b). In cases where mirror clamp control is difficult and suppression circuit (b) cannot be chosen, (c) and (d) could be combined, and it would be necessary to study overall system efficiency and perform optimization.

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