Verification of Loss Reduction Using Latest-Generation SiC MOSFETs

In electric vehicles (EVs), data centers, base stations, smart grids, and other products and applications, there have been prominent trends toward power supplies with higher voltages and larger capacities in order to further improve convenience. But in light of the need to grapple with global-scale environmental problems, reduction of energy losses has become an urgent issue. These applications convert a power feed into an appropriate power level for use, but energy losses occur in the power conversion process. In high-voltage, high-power applications, this loss is far from negligible, and of late there have been urgent demands for energy loss reduction, that is, for higher efficiencies in power conversion.

At present, the measure attracting the most attention as a means of boosting power conversion efficiencies is SiC power semiconductors that are capable of high-frequency operation and combine high voltages and high power levels with low energy losses. ROHM has been supplying SiC power semiconductors for use in a wide range of applications. The company has already released 4th-generation SiC MOSFETs, greatly contributing to reduction of losses in power conversion.

In this article, loss reduction through the use of the latest 4th-generation SiC MOSFETs is explained, with reference to basic buck DC-DC converters and EV applications.

Features of 4th-Generation SiC MOSFETs

ROHM’s SiC MOSFETs have already advanced to a 4th generation. The trench gate structure that was established in the 3rd generation was further developed, and still lower on-resistances and faster switching characteristics were achieved. Prior to explaining the advantages of the 4th-generation SiC MOSFETs, the features of these products are first explained.

Improved Short-Circuit Withstand Time, Lower On-Resistance Achieved

4th-generation SiC MOSFETs offer the improved short-circuit withstand time required for EV traction inverters and other equipment through further refinements to ROHM’s proprietary double-trench structure, and feature an on-resistance reduced roughly 40% compared with 3rd-generation products. The on-resistance of 4th-generation devices is among the best in the industry*.
* ROHM survey, February 2022

Dramatic Reduction of Parasitic Capacitance, Lower Switching Losses

By greatly reducing the gate-drain capacitance (C_GD), switching losses can be cut by about 50% compared with 3rd-generation devices.

Driving with a 15 V Gate-Source Voltage for Improved Ease of Design

4th-generation SiC MOSFETs have a lowered gate-source voltage V_GS for MOSFET driving of only 15 V. By reducing the driving voltage from the 18 V for 3rd-generation devices to 15 V, application design is made easier.

Related Information

Regarding SiC MOSFET lineup and support information, please refer to the following pages.

• ◆ SiC MOSFET Product Page
  https://www.rohm.com/products/sic-power-devices/sic-mosfet
• ◆ 4th Gen SiC MOSFETs Details
  https://www.rohm.com/products/sic-power-devices/sic-mosfet#supportInfo
• ◆ Supporting Content for ROHM 4th Gen SiC MOSFETs
  https://www.rohm.com/products/sic-power-devices/sic-mosfet#anc-02

Effects of Using 4th-Generation SiC MOSFETs in Buck DC-DC Converters

From this point, the effects of use of 4th-generation SiC MOSFETs in basic buck DC-DC converters are explained.

In “Circuit Operation Principles and Loss Analysis,” the mechanisms of occurrence of switching losses, conduction losses, body diode losses, recovery losses, and so on are explained. In the subsequent “Verification of Actual DC-DC Converters,” actual equipment verification is performed using an evaluation board to demonstrate the effect in improving efficiency when 4th-generation SiC MOSFETs are used.

Circuit Operation Principles and Loss Analysis

4th-generation SiC MOSFETs offer improvements over 3rd-generation devices, particularly with respect to speed of switching. This greatly contributes to reduced switching losses. Figure 3(a) is a block diagram of a buck DC-DC converter; Figure 3(b) shows the switching waveforms of same.

As shown in Fig. 3(b), losses in power devices S_H and S_L in a DC-DC converter consist of switching losses P_sw, conduction losses P_cond, body diode losses P_body recovery losses P_Qrr and C_oss losses. (*Because the C_oss loss is minuscule, it is omitted in the figure.)

Switching losses are generally indicated on data sheets as the energy per E_on and E_off pulse. These are convenient yardsticks to use when estimating rough losses in the initial design stage. In detailed design, losses must be determined rigorously under conditions of high-voltage input and high frequencies. Gate voltage values, the sink/source resistance values of gate drivers, external gate resistance values, and other values several ohms in magnitude affect switching times (T_rise/T_fall) at the level of several nanoseconds. Because losses differ greatly as a result, optimal design of a gate driver is connected with utilization of the high-speed switching characteristics of SiC MOSFETs.

Losses Occurring in High Side SiC MOSFETs SH

Switching losses occur only in the high side SiC MOSFET S_H, and are expressed as in equation (1). The mechanism of these losses is explained below.

\(P_{sw} = \frac{1}{2} V_{in} I_1 T_{rise} f_{sw} + \frac{1}{2} V_{in} I_2 T_{fall} f_{sw}\)　(1)

In State 1 (referring to the number of an interval T in Fig. 3(b); similarly below) a gate voltage V_GS is applied to the high side SiC MOSFET (S_H), and when in State 2 the V_GS exceeds the threshold voltage V_GS(th), an inductor current rapidly begins to flow into the S_H channel, and a load current I_o is reached in the few nanoseconds that elapse until V_GS(on) (the plateau voltage) is reached. During State 3 (the plateau interval), the channel turns on and V_DS reaches 0 V. These intervals State 2 and State 3 constitute the switching interval T_rise at turn-on of equation (2) below. In equation (2), the charge amount in State 2 is estimated from Q_gs, which does not normally appear on data sheets, adjusted by a coefficient k (normally k is from 1/3 to 1/4).

Further, the gate current I_{g_on} is determined by the potential difference between the gate driver voltage V_GS and the gate on voltage V_GS(on) and the resistance fraction between them, and so is given by equation (3). In the equation, R_src is the source resistance of the gate driver, R_{g_ext} is the external gate resistance, and R_{g_int} represents the internal gate resistance of the SiC MOSFET.

\(T_{rise} = \frac{\frac{1}{k} Q_{gs} + Q_{gd}}{I_{g\_on}}\)　(2)

\(I_{g\_on} = \frac{V_{GS} – V_{GS(on)}}{R_{src} + R_{g\_ext} + R_{g\_int}}\)　(3)

(State 4 is described below)

The gate voltage falls and the turn-off state (States 5 and 6) is entered. This T_fall interval is expressed by equation (4). Here it should be noted that the equation for the gate current I_{g_off} in the T_fall interval has only V_GS(on) in the numerator, as indicated in equation (5). In general, the turn-off time is slightly longer. In the latter equation, R_snk is the sink resistance.

\(T_{fall} = \frac{\frac{1}{k} Q_{gs} + Q_{gd}}{I_{g\_off}}\)　(4)

\(I_{g\_off} = \frac{V_{GS(on)}}{R_{src} + R_{g\_ext} + R_{g\_int}}\)　(5)

If the load can be regarded as a constant current source such as an inductor, the switching loss P_sw in equation (1) has a factor of 1/2 because the timing of the change in the current waveform I_D and the voltage waveform V_DS do not overlap.

Further, during this T_rise interval the electric charge accumulated in the drain-source capacitance C_ossH is shorted by the channel, so that the charge/discharge loss P_cossH expressed by equation (6) occurs.

\(P_{Coss\_H} = \frac{1}{2} C_{Coss\_H} \cdot V_{in}^2 \cdot f_{sw}\)　(6)

In State 4, the loss that occurs while the high side SiC MOSFET S_H is completely turned on is the conduction loss P_condH (equation 7). At this time, the effective current is given by equation (8), using the time ratio D (=V_o/V_in).

\(P_{cond\_H} = I_{SH\_rms}^{\hspace{2em} 2} \cdot R_{DS(on)}\)　(7)

\(I_{SH\_rms} = \sqrt{D \left( I_0^2 + \frac{\Delta I_L^2}{12} \right)}\)　(8)

These are the switching loss, conduction loss, and C_oss loss that occur in the high side SiC MOSFET S_H.

Losses Occurring in Low Side SiC MOSFET SL

Next, the losses occurring in the low side SiC MOSFET S_L are explained.

States 7, 11, and 1 are dead time intervals. A loss occurs due to the current conducting through the body diode of the low side SiC MOSFET SL (equation 9).

\(P_{body} = I_1 \cdot V_F \cdot T_{dead1} \cdot f_{sw} + I_2 \cdot V_F \cdot T_{dead2} \cdot f_{sw}\)　(9)

In States 8 to 10, conduction losses occur in the low side SiC MOSFET S_L (equation 10). The effective current at this time is given by equation (11).

\(P_{cond\_L} = I_{SL\_rms}^{\hspace{2em} 2} \cdot R_{DS(on)}\)　(10)

\(I_{SL\_rms} = \sqrt{(1 – D) \left( I_0^2 + \frac{\Delta I_L^2}{12} \right)}\)　(11)

The charge/discharge loss of C_oss in the low-side SiC MOSFET S_L is usually ignored because when the S_L turns on (State 8), the charge of C_oss is already discharged by the inductor current I_L, resulting in ZVS (Zero Voltage Switching).

The above are the losses occurring in the low side SiC MOSFET S_L.

Recovery Loss PQrr

The timing with which the recovery loss P_Qrr occurs is State 3; this loss arises from the recovery characteristic of the body diode of the low side SiC MOSFET S_L (equation 12). This loss is divided among the high side SiC MOSFET S_H and the low side SiC MOSFET S_L, but for simplicity, here they are combined as a high side loss.

\(P_{Qrr} = 0.5 \cdot V_{in} \cdot Q_{rr} \cdot f_{sw}\)　(12)

Total Loss

From the above, the total losses in the high side SiC MOSFET S_H and in the low side SiC MOSFET S_L are given by equations (13) and (14) respectively.

\(P_{SH} = P_{sw} + P_{cond\_H} + P_{Coss\_H} + P_{Qrr}\)　(13)

\(P_{SL} = P_{cond\_L} + P_{body}\)　(14)

In particular, where switching losses P_sw are concerned, from equations (2) and (4) we see that the smaller the value of Qgd (the charge amount in the mirror interval that charges the gate-drain capacitance), the shorter are the T_rise and T_fall times, so that the switching loss P_sw of equation (1) is reduced. 4th-generation SiC MOSFETs are able to lower switching losses due to the value of Qgd, which is reduced by about half compared with their 3rd-generation counterparts.

This means that one can expect loss reductions in DC-DC converters with high switching frequencies, and in EVs with their large fluctuations in loading but light averaged loads in typical driving. As a result, cruising ranges can be extended, and running costs are reduced. These are merits gained through the use of 4th-generation SiC MOSFETs, and result in major advantages for end users.

Verification with Actual DC-DC Converters

In order to confirm that the loss analysis explained in the above section is reflected in actual DC-DC converters, 4th-generation SiC MOSFETs were installed in a buck DC-DC converter with the specifications shown below, and verification with actual DC-DC converters was performed. Table 1 shows the specifications of the DC-DC converter and the SiC devices. As the external gate resistor R_{g_ext} that adjusts the switching speed, a 3.3 Ω resistor was used, striking a balance between fast switching and suppression of ringing and surges. Figure 4 shows (a) the DC-DC converter circuit, and (b) the evaluation board (with internal decoupling capacitor) for the 4th-generation SiC MOSFETs used in the half-bridge section. The inductor L, output capacitor CO, and input bulk capacitor are external components. For comparison, 3rd-generation SiC MOSFETs were also used.

Figure 5 shows the measured V_GS, V_DS, and I_D waveforms at the times of turn-on and turn-off at 50 kHz (waveforms on the right). The turn-on waveforms (the parts of the right-side waveforms surrounded by the green dashed line) are shown enlarged on the left. From the enlarged waveforms we see that the turn-on rise time T_rise is extremely fast, at about 20 ns.

Figure 6 shows measured results for the efficiency (left side) and losses (right side) of the DC-DC converter. Under light loading (near 1 kW), efficiency is greatly improved due to the small switching losses that, as fixed losses, are a feature of 4th-generation SiC MOSFETs. Moreover, we see that under heavier loads (around 5 kW), losses using the 4th-generation devices are improved by at least 15 W over the earlier 3rd-generation products.

Figure 7 shows the results of theoretical analysis of the breakdown of DC-DC converter losses. These results corroborate the finding that losses are improved by about 15 W. In particular, we see that the high side SiC MOSFET (S_H) switching losses and recovery losses P_Qrr are sharply reduced, contributing to the improvement in the overall loss figure.

Effect of Using 4th-Generation SiC MOSFETs in EV Applications

In succession to verification using actual buck DC-DC converters, here the advantages of using 4th-generation SiC MOSFETs in power solutions for EVs (electric automobiles) are presented as a specific application example.

EV power conversion is achieved using an OBC (onboard charger), auxiliary isolated DC-DC converter, boost DC-DC converter, and traction inverter. Where the traction inverter is concerned in particular, simulated running tests are performed using a motor test bench to explain how 4th-generation SiC MOSFET characteristics confer advantages to the user. In addition, we will explain the efficiency improvement gained by using 4th-generation SiC MOSFETs in the Totem-pole PFC constituting the OBC on an actual board.

EV Applications

EVs or electric vehicles have various forms. As shown in Figure 8, they include BEVs (battery electric vehicles), HEVs (hybrid vehicles), PHEVs (plug-in hybrid vehicles), series HEVs (series hybrids), and others, with different power architectures according to the respective applications. Attracting particular attention of late is the power architecture of BEVs with a battery voltage of 400 V or 800 V supporting bidirectional and rapid charging.

Figure 9 shows, as an example, the block diagram of the BEV power architecture. The OBC (onboard charger) is a hot topic topology with bidirectional Totem-pole PFC and bidirectional CLLC (symmetric LLC), assuming V2G (vehicle-to-grid) charging. The power output from the OBC is supplied to the auxiliary DC-DC converter, the battery, the boost converter to the inverter and the main traction inverter.

Simulated Running Tests in Traction Inverters

Here the basic operation of a traction inverter, as well as an evaluation system for EVs (motor test bench testing environment), are explained. The testing results are used to perform running simulations in accordance with the WLTC fuel consumption testing method for passenger vehicles, as an example of improvement of electricity cost through the use of 4th-generation SiC MOSFETs.

Inverter Circuit Operation

With advances in mechatronic integration (motors, reduction gears, inverters), the importance of reducing losses has continued to mount in order to obtain inverters capable of handling high voltages and providing high outputs while remaining small and lightweight. This is because it directly impacts the electricity cost performance of EVs.

As shown in Figure 10, the traction inverter converts the DC power provided by the battery into 3-phase AC power to drive the motor in the powertrain. The inverter is formed from three legs, each having a half-bridge configuration. The 3-phase AC waveforms are set using a signal wave (reference sine wave) with a frequency synchronized with the rotation rate of the motor, and a triangular wave (modulation wave) is set using a carrier frequency that determines the switching frequency. The voltage supplied to the motor is determined by changing the levels of the 3-phase AC and triangular waves when generating the PWM signal.

Motor Test Bench Testing Environment

Table 2 shows the main specifications of the motor test bench and the test inverter. The test inverter employed 2-in-1 power modules in which are mounted 4th-generation SiC MOSFET bare chips.

Figure 11 shows the testing environment of the motor test bench, Figure 12 shows the test (DUT) inverter, and Figure 13 is a block diagram of the control system. The test motor is driven by the DUT inverter via 3-phase uvw power lines. The test motor is connected to a load motor, and the load motor is controlled by the load torque according to the running resistance calculated from the vehicle parameters, which enables the simulated running experiment with the desired vehicle parameters. The running resistance takes into account of the air resistance FAD, rolling resistance FRR, gradient resistance FRG, and acceleration resistance FACC, as shown in Figure 14 and equations (15) to (18).

International Standard WLTC Mode Fuel Consumption Tests for Simulated Running

The WLTC (Worldwide harmonized Light duty driving Test Cycle) shown in Figure 15 is a running cycle stipulated in the WLTP (Worldwide harmonized Light vehicles Test Procedure) for exhaust emissions and fuel consumption testing of passenger vehicles and the like, adopted as a GTR (Global Technical Regulation) at the 162nd World Forum on Harmonization of Vehicle Standards (WP29) held in 2014 by the United Nations Economic Commission for Europe. This cycle is made up of low, middle, high, and extra-high speed phases; in Japan, test vehicles are driven in the running cycle except for the extra-high phase to measure exhaust emissions and fuel consumption.

Using the above-described motor test bench, conditions for simulated running tests based on the WLTC running cycle were input, and running electricity cost tests were conducted for cases in which 4th-generation SiC MOSFETs and IGBTs were used in the inverter.

Electricity cost test results assuming a C segment class EV are shown in Figure 16. It was verified that when 4th-generation SiC MOSFETs are substituted for the conventional IGBTs, electricity cost was improved in all speed phases of the WLTC running cycle. Total electricity cost was improved by about 6% compared to when using IGBTs, and roughly 10% in urban mode.

For reference, Figure 17 shows an inverter efficiency bar graph (with efficiency information added based on NT curves). These results also show that efficiency is greatly improved in the high-torque and low-rpm range that appears prominently when running in urban areas.

Below are shown an example of user advantages resulting from improvements in electricity cost. When the reductions in running cost (electric bill) for a given travel distance and the reduction of onboard battery capacity are considered, advantages should be clear. Table 3 shows an example trial-calculated for suburbs mode. Compared with IGBTs, the improvement in electricity cost is 5.5%, for a savings of 2000 yen when traveling a distance of 10,000 km, or 55,000 yen for a vehicle with a 100 kWh battery installed (Figure 18).

Evaluation Using Actual Totem-pole PFC

The Totem-pole PFC is a topology that has been attracting a large amount of attention of late in the form of a PFC converter capable of high efficiencies. The V2G (Vehicle to Grid) is also being studied around the world to stabilize microgrid systems and contribute the supply-demand balance, and bidirectional operation has taken on increased importance.

Totem-pole PFC Circuit Operation

Figure 19 is a circuit block diagram. The left leg (S₁, S₂) is used for high-frequency switching, and the right leg (S₃, S₄) is for commercial frequency (low frequency) rectification. By using synchronous rectification for S₃ and S₄, the bidirectional operation needed for V2G becomes possible.

Figure 20 shows operation diagrams for different states. During the positive half-cycle of the commercial AC, the Totem-pole low-side switch (S₂) performs high-frequency switching (period D in (a)) as a boost converter. At this time, S₁ performs rectification (period 1-D in (b)), but if recovery in the body diode is slow, large power losses occur. SiC MOSFETs have an extremely fast recovery time, and the effect of such power losses can be kept small, making them extremely well-suited as power devices in Totem-pole PFC circuits.

Next, in the negative half-cycle, the Totem-pole high-side switch (S₁) performs high-frequency switching as a boost converter (period D in (c)), and S₂ performs rectification (period 1-D in (d)). S₃ and S₄ switch at every half-cycle of the commercial AC.

Evaluation Using Actual Totem-pole PFC

In order to verify that 4th-generation SiC MOSFETs are effective for reducing losses in a Totem-pole PFC circuit, experiments were conducted using the actual board. Table 4 shows the PFC evaluation conditions and the main specifications of the SiC devices used. When the output voltage was 400 V, a SiC MOSFET with 750 V withstand voltage was appropriate. Here, SCT4045DR devices were used.

Figure 21 shows switching waveforms on the actual board. We can see that turn-on and turn-off occur over very short times of 20 to 30 ns.

Figure 22 shows measurement results for efficiency. When 4th-generation SiC MOSFETs are used, high efficiencies of over 98% are achieved for a half load of 1.5 kW, and 97.6% for a full load of 3 kW.