2020.10.07 SiC Power Device
We further explain the gate driving circuit with a SiC MOSFET bridge configuration explained in the previous article, and discuss turn-on and turn-off operation of the circuit.
Gate Driving Circuit with a SiC MOSFET Bridge Configuration
The manners in which VDS and ID of the LS (low-side) SiC MOSFET change are different at turn-on and at turn-off. When considering the effect of these changes on the gate-source voltage (VGS), our starting point is an equivalent circuit that includes the parasitic components of the gate driving circuit.
The diagram on the right is the equivalent circuit of the gate driving circuit and SiC MOSFET on which the analysis is based. In the gate driving circuit there is a gate signal (VG), and there are also the resistance (RG_INT) due to the gate line within the SiC MOSFET, as well as the source inductance (LSOURCE) of the SiC MOSFET package, as well as the inductance (LTRACE) of the gate circuit trace and the external gate resistance (RG_EXT).
The polarities of voltages and currents are taken to be positive in the direction indicated by the gate current (IG) and the drain current (ID) in the equivalent circuit diagram, and VGS and VDS are defined with the source pin as reference.
The gate line within the SiC MOSFET also has an associated inductance, but it is small compared with LTRACE, and so is here omitted.
Turn-on and Turn-off Operation
In order to understand turn-on and turn-off operation in the bridge circuit, we explain in detail the voltage and current waveforms for each of the SiC MOSFETs in the bridge circuit shown previously. The following waveform diagram is the same as was previously shown; it should be examined together with the previously shown equivalent circuit.
When a positive voltage VG is applied as the LS-side gate signal in order to turn on the LS side, charging of the gate-source capacitance (CGS) begins and VGS rises, and upon reaching the SiC MOSFET gate threshold voltage (VGS(th)), ID begins to flow on the LS side, and simultaneously the ID on the HS side, flowing from the source toward the drain, begins to decrease. This time interval is the previously defined interval T1 (indicated at the bottom of the waveform diagram).
Next, when the HS-side ID goes to zero and the parasitic diode is turned off, the midpoint voltage (VSW) begins to drop, and simultaneously the HS-side drain-source capacitance (CDS) and drain-gate capacitance (CGD) are charged (T2 in the waveform diagram). After completion of this charging of CDS + CGD on the HS side (while the LS side is discharged), when the LS-side VGS has reached a certain voltage, the LS-side turn-on operation is completed.
On the other hand, the turn-off operation begins with turn-off on the LS side; the charge accumulated on CGS on the LS side begins to be discharged, and when the SiC MOSFET plateau voltage is reached (when the mirror effect interval is entered), the LS-side VDS begins to rise, and simultaneously VSW rises.
At this time, nearly all the load current is still flowing on the LS side (T4 in the waveform diagram), and a commutation current is not yet flowing in the HS-side parasitic diode. When charging of the LS-side CDS + CGD (while the HS side is discharging) is completed, VSW exceeds the input voltage (E), the HS-side parasitic diode is turned on, and the LS-side ID begins commutation to the HS side (T5 in the waveform diagram).
The LS-side ID at long last reaches zero, entering a dead time interval (T6 in the waveform diagram), and a positive VG is applied as the gate signal to the HS-side MOSFET to turn it on, constituting a synchronous operation period (T7 in the waveform diagram).
In this series of switching operations, various gate current flows arising from changes in VDS and ID of the HS-side and LS-side MOSFETs, and these appear as changes in VGS that are different from the applied signal VG. This will be explained in the next article.
・The manners of changes in VDS and ID are different during turn-on and during turn-off.
・The effects of these changes on VGS are considered based on an equivalent circuit that includes the parasitic components of the gate driving circuit.