SiC Power Device｜Application
Guidelines Relating to PCB Layout for Surge Suppression Circuits
2023.10.25
Points of this article
・In designing the PCB layout for a surge suppression circuit, consideration must be paid to switching large currents at high speed.
・Parasitic capacitances, inductances, and resistances should be minimized.
・Return line loops should be minimized to deal with EMI.
Up to this point, positive voltage surge countermeasures and negative voltage surge countermeasures have been explained. This article explains points requiring attention relating to PCB layout when implementing the countermeasures in surge suppression circuits.
Surges occurring in gate-source voltages have already been explained in detail in the previously mentioned “SiC MOSFETs: Behavior of Gate-Source Voltage in a Bridge Configuration” in the Applications Edition of the Tech Web Basic Knowledge section on SiC Power Devices, and should be referenced as necessary.
Guidelines Relating to PCB Layout for Surge Suppression Circuits
Because the placement of components and the wiring pattern layout of a surge suppression circuit impact the efficiency of surge suppression, there are matters that demand attention if the desired efficacy is to be achieved. We begin by presenting an example of a surge suppression circuit and a PCB layout. The circuit diagram has been used before; this is only one side of the original circuit. Hence on the PCB there are two such circuits, for HS and for LS.
Example of surge suppression circuit and PCB layout
On this PCB, the HS MOSFET of the bridge configuration is on the upper side, and the LS MOSFET is positioned on the lower side; the MOSFETs are arranged such that the gate terminal and driver source terminal are below the MOSFET in the board photo. The circuits to suppress VGS surge voltages are positioned very close to the gate terminals, with the connection distance minimized. These positions were chosen in order to minimize parasitic capacitances, inductances, and resistances.
Next, we present the pattern layout of the surge suppression circuits.
When providing multiple surge suppression circuits, the mounting position of the mirror clamping MOSFET (Q2) must first be determined with the highest priority. Next, the negative surge clamping SBD (D2) and its bypass capacitor (C2) are positioned, and then the positions of the positive surge clamping SBD (D3) and its bypass capacitor (C3), and of the false turn-on suppression capacitor (C1), are determined in order. This is because if the mirror clamping MOSFET in particular is positioned just a few centimeters away, the inductance of the wiring can greatly detract from the surge suppression effectiveness.
Moreover, it is also very important to minimize the loop consisting of the surge suppression circuit return line (the return line from the driver source terminal) and the wiring in the surge suppression circuit. This is because the high-speed switching of SiC MOSFETs causes powerful EMI as a result of the di/dt occurring in the drain current ID, and so it is important that this wiring loop not be affected by this EMI insofar as possible. The PCB used in these evaluations has a four-layer structure, in which all of Layer 2 is used for return lines. Hence the return line can be positioned directly below the surge suppression circuit, so that the loop area can be minimized.
Bypass capacitors are provided together with the clamping SBDs; if the impedance from the driving power supply is sufficiently low, they are unnecessary, but in general it is frequently the case that the power source is some distance away, and in such cases a bypass capacitor must be positioned close to an SBD so that the SBD can operate at a lower impedance. When selecting these capacitors, the impedance characteristic should be carefully considered, and capacitors with a resonance point in the tens of MHz band should be chosen (0.1 μF, size 1.0×0.5 mm).
【Download Documents】 Basics of SiC Power Devices
This handbook explains the physical properties and advantages of SiC, the differences in characteristics and usage of SiC Schottky barrier diodes and SiC MOSFETs with a comparison to Si devices, and includes a description of full SiC modules with various advantages.
SiC Power Device
Basic
- What are SiC Schottky barrier diodes? ? Introduction
- What are SiC-MOSFETs? – SiC-MOSFET Features
- What are Full-SiC Power Modules?
- Summary
- Introduction
- What is silicon carbide?
Application
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Introduction
- SiC MOSFET Bridge Configuration
- SiC MOSFET Gate Driving Circuit and Turn-On/Turn-Off Operation
- Currents and Voltages Occurring Due to Switching in Bridge Circuits
- Behavior of the Gate-Source Voltage During Low-side Switch Turn-on
- Behavior of the Gate-Source Voltage During Low-side Switch Turn-off
- Summary
- SiC MOSFETs: Method for Determining Losses from Switching Waveforms
-
SiC MOSFETs： Snubber Circuit Designs ーIntroductionー
- Non-Discharge RCD Snubber Circuit Design
- Surges Occurring between Drain and Source
- Types and Selection of Snubber Circuits
- C Snubber Circuit Design
- RC Snubber Circuit Design
- Discharge RCD Snubber Circuit Design
- Non-Discharge RCD Snubber Circuit Design
- Differences in Surge Occurrence Depending on Package
- SiC MOSFETs： Snubber Circuit Designs ーSummaryー
- Points to Note When Measuring SiC MOSFET Gate-Source Voltages: General Measurement Methods
-
Conventional MOSFET Driving Method
- Packages Provided with Driver Source Terminals
- Differences Made by and Benefits of a Driver Source Pin
- Benefits of a Driver Source Terminal: Comparisons Using Double Pulse Tests
- Behavior of Gate-Source Voltages when in a Bridge Configuration: Behavior at Turn-on
- Behavior of Gate-Source Voltages when in a Bridge Configuration: Behavior at Turn-off
- Points to be Noted Relating to Board Wiring Layout Key Points of This Article
- Verification of Loss Reduction Using Latest-Generation SiC MOSFETs
- About Surges in Gate-Source Voltages
Product Information
- SiC Schottky Barrier Diodes
- SiC MOSFET
- SiC Power Modules
- SiC Schottky barrier diode Bare Die
- SiC MOSFET Bare Die
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