Transistors｜Evaluation

Guidelines Relating to Operation of Switching Elements Under Light Loading

2021.10.27

Points of this article

・Under light loading, currents are small, and the accumulated energy in L_S is small, so that it is entirely possible that switching operation may begin without complete C_OSS charging/discharging, as a result of which ZVS operation is not possible, and MOSFET turn-on losses readily occur.

・Due to incomplete C_OSS charging/discharging, V_DS may remain, and so in order to prevent shoot-through currents caused by upper/lower arm short-circuits, it is important that the dead time be set appropriately.

・Because a shoot-through current may flow depending on the capacitance ratio of C_GD and C_GS of a MOSFET, it is important that MOSFETs with an appropriate capacitance ratio be selected.

Because under light loading currents are small and the energy accumulated in L_S is small, there is increased possibility that switching operation may begin without complete charge and discharge of C_OSS in the lagging leg. Consequently ZVS operation is not achieved and MOSFET turn-on losses occur more readily.

On the other hand, during charging and discharging of the C_OSS capacitors of the leading leg MOSFETs, energy is being sent to the secondary side via the transformer. When, as in the previous discussion, the conditions for ZVS establishment are considered in terms of energy balance, taking Mode (2) as an example, if the transformer windings ratio is n, then the condition for ZVS in the leading leg can be expressed by the following inequality. Here I_L2 is the I_L at the end of Mode (1), and E_{OSS_Q1} and E_{OSS_Q2} are respectively the energy necessary for charge/discharge completion of the C_OSS capacitors of Q1 and Q2.

In actual circuit operation, a dead time must be provided in order to prevent upper and lower arm short-circuits. As explained above, under light loading it is possible that charge/discharge of lagging leg MOSFETs is not completed, that is, drain voltages V_DS may remain (resulting in hard switching); consequently, depending on how the dead time is set, MOSFET turn-on losses in lagging leg may increase. Hence care must be taken when setting the dead time.

The following is a summary diagram of turn-on behavior when the dead time is and is not optimized.

When the dead time is not optimized, an instantaneous large drain current I_D flows. This is a consequence of two currents: a shoot-through current resulting when the gate-source voltage V_GS exceeds the threshold voltage because of the capacitance ratio of the gate-drain capacitance C_GD and the gate-source capacitance C_GS, and the current charging the C_OSS of the opposite arm MOSFET. Of these, the latter, the current charging the C_OSS, always occurs during hard switching operation, but the former, the shoot-through current, can be prevented in advance by appropriately setting the capacitance ratio of C_GD and C_GS for the MOSFET. Hence it is important to choose MOSFETs that have an appropriate C_GD to C_GS capacitance ratio.

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