Si Power Device|Basic

Confirmation that Operation is within the SOA Derated at the Actual Operating Temperature


Points of this article

・An SOA graph is for data at Ta=25°C, and so the SOA must be derated according to the temperature at which the transistor will actually be used.

・As the derating rate, the derating rate for allowable power dissipation is used.

In this chapter, we explain methods and procedures for determining whether or not a selected transistor is appropriate in actual operation.

This time, we explain ④“Confirmation that operation is within the SOA derated at the ambient operating temperature” in the flowchart on the right.


④Confirmation that Operation is within the SOA Derated at the Ambient Operating Temperature

In the previous section, the concept of SOA was explained, together with the use of graphs and the like, and points to be considered were also discussed. This time, in connection with one of those points for consideration, that the data of a SOA graph is for an ambient temperature Ta of 25°C, we calculate the SOA at the temperature of actual use, and confirm the proper conditions of transistor use. We have already used the term “derated” in the title for this section because in nearly all cases, the actual ambient operating temperature is higher than 25°C, and so in effect derating of the 25°C SOA is performed.

What is SOA Derating?

By now the reader should understand the meaning of derating. The meaning is similar for SOA as well; data for conditions of 25°C must be adjusted, further reducing the current and voltage to obtain the SOA for the higher temperature at which the transistor will actually be used. Below are graphs describing derating of the SOA of a bipolar transistor and a MOSFET.


SOA derating is basically considered in terms of the allowable power dissipation, that is, the heat generated, and ultimately the Tjmax. General examples appear in the above graphs; in the case of the bipolar transistor, derating is 0.8%/°C in the thermally limited region, and 0.5%/°C in the secondary breakdown region. For the MOSFET, the derating of the maximum current due to increased on-resistance and the derating of 0.8%/°C in the thermally limited region are shown.

This is explained in a bit more detail below. The following, excerpted from data sheets, are the SOA graph and a graph indicating derating of the allowable power dissipation for the MOSFET R6020ENZ which is used as an example in this chapter.


Here, assume that the Tj of the actual transistor is 75°C. Previously we had been discussing the ambient temperature, that is, Ta, but when considering allowable losses in a transistor, ultimately it is necessary to consider Tj.

Let us take a moment to examine the relationship with temperature. Among matters requiring consideration that were discussed the last time was the condition that “data must be for single pulses”. In cases of continuous use, conditions are somewhat troublesome, but by stipulating the condition of single pulses, it is possible to set Ta?Tj. This is a general interpretation, based on the consideration that for a pulse of short duration, there is almost no rise in the transistor chip temperature. In parameter tests for semiconductor devices, also including transistors, when heat generation is also considered, in many cases pulse tests assumed that Ta?Tj. Hence it is assumed that the data for this SOA is Ta?Tj?25°C.

However, for transistors it is necessary to determine Tj from the power dissipation and the package thermal resistance θja and Ta, or else θjc and Tc. These thermal calculations are of a general nature, and so are here omitted.

From the derating curve for the allowable power dissipation in the upper left graph, we see at Tj=75°C relative to Tj=25°C, derating to 60% is necessary. One need only use this rate to perform derating as in the calculation example. If necessary, by computing the derating rate, (100%-60%)/|25°C-75°C| =0.8%/°C, calculations can be performed immediately, and the SOA derating curve may be drawn as indicated by the blue line in the graph.

Finally, the actual conditions of use of the transistor must be confirmed to be within the derated SOA, and whether the usage conditions are appropriate must be judged.

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