Estimation of Heat Dissipation Area in Surface Mounting and Points to be Noted

Up to this point, methods for estimating T_J using thermal resistance and thermal characterization parameters have been explained. In this article, a method is described for estimating the heat dissipation area in surface mounting in order to ensure that T_Jmax is obeyed, and important points relating to the thermal consequences of component layout are explained.

Component Layout and Thermal Interference

Demands for miniaturization in recent years have led to the need for circuit boards that are as small as possible, and component mounting densities are trending upwards. However, components that emit heat, which in this case are ICs, require use of the mounting board for heat dissipation, and to this end a certain area is needed. If this board area is not secured, thermal resistance is higher and heat generation becomes excessive. If heat-generating ICs are mounted in close proximity, interference by their generated heat may cause increases in temperature.

The figures below illustrate heat dissipation paths of a surface-mounted IC, and heat dissipation when heat-generating ICs are in close proximity.

Heat generated by an IC is conducted laterally (over a board area) and vertically (through the board thickness) and is dissipated. However, when ICs are densely mounted, there is mutual interference by heat dissipation in lateral directions in particular–the heat has nowhere to go. Hence temperature increases result.

Estimating the Board Area Needed for Heat Dissipation

In order to ensure that a surface-mounted IC can have a thermal resistance that remains within the T_Jmax limit, a corresponding heat dissipation area is necessary. In addition, it is also important to ensure that thermal interference does not occur. The diagram below illustrates the interval needed so that there is no thermal interference. After ensuring that this minimum condition is satisfied, the required heat dissipation area is estimated using a graph of the relationship between θ_JA and the copper foil area.

As the diagram indicates, the minimum interval is set such that there is no interference between straight lines inclined 45° from the edges of ICs to the board surface. Next, the required θ_JA for the conditions of use is determined.

Conditions example: IC power consumption=1 W, maximum ambient temperature T_A(HT)=85°C, maximum allowed T_J=140°C

In this way, IC intervals that avoid heat interference and a sufficient heat dissipation area are secured, and then the final placement of ICs is studied.