In relation to the Power Supply Sequence Specification ①, in the article before the last and in the previous article, sequence operations upon power turn-on and shutoff were explained. In this article, an actual circuit example to realize these operations as well as component value calculations for circuit settings are explained.
Below is shown an example of a circuit that realizes the power supply sequence. For the three DCDC systems 1 to 3, switching regulators or linear regulators (LDOs) are assumed. Each DCDC has an enable pin (EN) that can turn the output on and off.
Example of a circuit to realize the Power Supply Sequence ①
There are four Power Good blocks; a BD4142HFV, which is a voltage monitoring IC, is used to implement Power Good functions. IC1 and IC3 are used to detect the rise of the DCDC output voltage to the setting value at power turn-on, and IC2 and IC4 detect voltage drop at power shutoff. Below, a Power Good circuit that includes the BD4142HFV internal functional block is shown.
Power Good function using a BD4142HFV
This IC incorporates a hysteretic comparator with a 0.5 V reference voltage (see the IC functional block), and the voltage to be detected can be set using an external resistive divider. IC1 and IC3, which detect the rise of DCDC output voltages, must be set according to the DC/DC output voltages. The detection voltage VPGOOD can be calculated using equation 1-1.
In this sequence circuit example, VOUT1 is 1.2 V, and PGOOD of IC1 is set to output a flag when 90% of the output voltage is reached. If the detection voltage is set too high, such as at 95%, when the output voltage drops momentarily due to a load fluctuation the PGOOD output may go to "L", so that a problem occurs when the later-stage DCDC is momentarily shut off. Detection voltages must be determined only after having understood DCDC load fluctuations and voltage drop (load response) characteristics.
At 90%, the detection voltage is 1.2 V × 0.9 = 1.08 V. The resistor value can be determined using equation 1-1. The calculated resistor values are already shown for IC1 in the circuit example; the resistance corresponding to R2 in equation 1-1 is R6 (15 kΩ) + R7 (82 Ω), and that corresponding to R3 is R8 (13 kΩ). Substituting these values, we see that they are the component values needed to obtain the desired 1.08 V.
As is seen from the equation, resistor values are determined relative to VPGOOD such that the voltage divided by R2 and R3 and applied to the IN pin is the internal reference voltage of 0.5 V. The voltage is determined by a resistor ratio, but this resistive voltage divider is also the DCDC load, and so it is appropriate to use resistor values in the 10 kΩ range. However, the sum of R2 and R3 is within 300 kΩ. For details, please refer to the data sheet.
Basic component values are determined in this way, but as part of design, tolerances for settings (detection voltages) must be confirmed. The detection voltage tolerance for the BD4142HFV is ±1.8%. Hence the range for PGOOD is from 88.4% (less than 90% by 1.8% of 90% = 90×0.982) to 91.6% (more than 90% by 1.8% of 90% = 90×1.018).
Moreover, there is a 10 mV hysteresis, so that the detection release voltage is 90%× (0.5 V - 10 mV)/0.5 V = 88.2%, and the range is 88.2%×0.982 = 86.6% to 88.2%×1.018 = 89.8%.
The BD4142HFV can impart a delay time tDELAY to the PGOOD flag output. In this case, a capacitor C2 is connected to the DLY pin. The delay time or the value of the capacitor C2 can be calculated using equation 1-2.
IC2 and IC4, the PGOOD pins of which operate upon power shutoff, release detection when the DCDC output voltage falls to about 0.5 V or lower (the PGOOD output changes from "H" to "L"). This utilizes the detection voltage, a basic setting in the BD4142HFV, without modification.
Discretely configured discharge circuits are connected to the DCDCs. As indicated by the diagram below, the circuits consist of NPN transistors and resistors. The first-stage transistor is a simple inverter circuit; the second stage is an open-collector switch. Turn-on of the second stage causes the remaining charge, mainly in the output capacitor, to be discharged at DCDC shutoff, rapidly causing VOUT to fall. The fall time of the output voltage is adjusted through the value of the resistor (R4 in the diagram below) series-connected to the collector of the second-stage transistor.
Diodes at different places in the sequence circuit are provided to govern logic operations. The forward voltage VF of a diode affects the voltage of an "L" level signal, and so a Schottky barrier diode with low VF is used to secure a "L" level voltage value.
The above has been an explanation of an entire circuit for realizing the Power Supply Sequence ①, as well as of Power Good blocks, discharge circuits and diodes which are peripheral circuits in addition to DCDCs.
・A circuit to realize the power supply sequence ① consists of 3 DCDCs, 4 Power Good blocks, 3 discharge circuits, and diodes.