From this point, we explain specific component layout. This time, we will focus on the third item below, "Placement of input capacitors and output diodes".
Placement of Input Capacitors and Output Diodes
The PCB layouts explained from this point on are based on the circuit on the right, which was used in the explanation of current paths. It would be useful to recall this circuit when viewing the PCB layout diagrams.
To begin with, an input capacitor and output diode are arranged on the board, as the most important components.
In "Important Points in PCB layout" described in “Overview of DC/DC Converter PCB Layout” at the beginning of this chapter, it was stated that input capacitors and diodes are placed on the same surface as IC pins, and as close to ICs as possible. This is a straightforward but extremely important point, and should always be born in mind.
In the case of a power supply with a small current capacity (IO ≤ 1 A), the capacitance value of the input capacitor is also small, and so a single ceramic capacitor may be used to serve as both CIN and CBYPASS. This is because ceramic capacitors with smaller capacitance values have better frequency characteristics. However, the frequency characteristic will differ depending on the ceramic capacitor, and so it is necessary to check the frequency characteristic of the component that is actually used.
A large-capacitance capacitor used as CIN will not generally have a particularly good frequency characteristic, as indicated below, and so a decoupling capacitor CBYPASS with a good frequency characteristic must be arranged in parallel with CIN.
A surface-mount type multilayer ceramic capacitor should be used as CBYPASS.
Well then, let's describe satisfactory and unsatisfactory examples while indicating the actual layout.
Figure 3-a shows a satisfactory input capacitor layout example. CBYPASS is positioned close to the IC pins, on the same board surface.
On the other hand, Figure 3-b is an example in which a compromise is made.
CBYPASS supplies most of the current in pulse form, and so it is thought that if the large-capacitance capacitor CIN is about 2 cm distant, as in Figure 3-b, there should be no problem; but even so, it is better to position the device "as close as possible to the IC", as explained at the beginning.
When, because of space limitations, CIN cannot be placed on the same surface as the IC, it can be positioned on the opposite side using vias as in Figure 3-c, on condition that CBYPASS is positioned correctly.
In this case, risks related to noise may be avoidable, however there is the possibility that the ripple voltage will increase under large currents due to the effect of the via resistance. It will be necessary to check these issues.
Figure 3-d. Unsatisfactory placement of the input capacitor: via inductance causes an increase in noise
In this layout, the via inductance component causes an increase in voltage noise, and so this kind of layout must never be used.
Figure 3-e shows a desirable layout for CBYPASS, CIN and the diode D1.
It is important that CBYPASS be placed close to the VIN pin and the GND pin of the IC.
However, in the case of a step-down converter, even if CBYPASS is placed very close to the IC, high frequencies in the hundreds of megahertz range are present on the ground side of CIN. For this reason, it is recommended that the ground of CIN and the ground of the output capacitor CO be separated by 1 to 2 cm.
The diode D1 is also placed close to the IC pins on the same surface. The shortest and widest wiring must be used to connect the diode directly to the IC switching pin and the GND pin.
If vias are used to place components on the rear surface, the effect of the via inductance cases an increase in noise, and therefore vias must never be used.
Figure 3-f is an example of an unsatisfactory diode layout.
Because there is some distance between CBYPASS and the IC VIN and GND pins, voltage noise/ringing occurs due to the effect of the wiring inductance.
The diode is distant from the IC switching pin and GND pin, and so the wiring inductance increases, spike noise becomes prominent.
Inappropriate placement of CBYPASS, that is, not placing it in proximity, results in increased parasitic inductance due to the wiring length and/or vias. This can cause large ringing accompanying switching.
Moreover, the loop leading to the input capacitor functions as an antenna to radiate noise to the surroundings.
The following waveforms are for cases in which CBYPASS is positioned 2 mm away and 10 mm away. The increase in ringing is clearly visible.
The above explanation has been rather simple and matter-of-fact, but that is because the consequences of a PCB layout are themselves quite simple and straightforward. In actual layout works, there will be cases in which compromises cannot be avoided. However, these compromises should be kept to a minimum, and the designer should always strive for an ideal layout.
・It is a good idea to begin with placement of the input capacitor and diode.
・As an inviolable rule, the input capacitor and diode must always be placed on the same surface as the IC pins, and as close to the IC as possible.
・Parasitic inductance is a cause of noise, and so use of vias should be studied carefully. Places where current is switched require careful attention.