Power Supply Sequence Specification②:Power Supply Sequence Specifications and Control Block Diagrams

From this article, we embark on an explanation of the power supply sequence circuit of a second example. Initially we confirm the power supply sequence specifications to be achieved, and study the circuit configuration using control blocks.

Power Supply Sequence Specification②

The power supply sequence specifications ② are, like ①, for sequencing of three power supply systems, but the sequences are different. The input and output voltage specifications, power supply configurations, and sequences are as follows.

The design for specification ② is based on three power supply ICs. As the power supply ICs, switching regulators (DC-DC converters) or linear regulators (LDOs) are assumed. The power supply ICs must have enable pins facilitating on/off control of the output.

Power is turned on in the order V_OUT1, V_OUT2, V_OUT3; when V_OUT1 is turned on and the voltage setting is reached, V_OUT2 is turned on, and when the voltage setting is similarly reached, V_OUT3 is turned on. Shutoff is performed similarly to turn-on in the order V_OUT1, V_OUT2, V_OUT3, with sequencing such that when V_OUT1 shutoff ends, V_OUT2 is shut off, and then V_OUT3 is shut off.

Control Block Diagram②

The control block diagram for implementing sequence specification ② is shown below.

For implementation of sequence specification ②, in addition to three power supply ICs, two Power Good functions, three Discharge functions, and pull-up resistors are required. The block diagram indicates the functions and operations in block form, but in the actual circuit, external components and the like are also required. Below, the various functions and roles are explained.

• ・DCDC 1, DCDC 2, and DCDC 3 are separate power supply ICs, the output of each of which is controlled via an enable (EN) pin.
• ・Power Good 1 and 2 monitor the DCDC output voltages during power turn-on, and upon reaching the target voltage, output a “High” (hereafter “H”) signal to the next DCDC to start up.
• ・Similarly during power shutoff, Power Good 1 and 2 monitor the DCDC output voltages, and when a voltage drops to the target voltage, output a “Low” (“L”) signal to the next DCDC to be shut off.
• ・The Discharge blocks cause the power supply sequencing to operate normally by rapidly discharging the electric charge that has been stored in the DCDC output capacitors at power shutoff to cause the output voltages to drop.

In this block diagram, the sections between EN and VOUT of DCDC blocks, between IN and PGOOD of Power Good blocks, and between IN and OUT of Discharge blocks, are designed using positive logic. That is, at “H” level, the DCDC blocks are in the enabled state, the Power Good blocks have arrived at their target voltages, and the Discharge block outputs are turned on. Also, the PGOOD pins (outputs) of the Power Good blocks and the OUT pins of the Discharge blocks are open-collector or open-drain type terminals.