In the DC/DC converter design edition "Board Layout of DC/DC Converters", we explained the matters described below. This time, by way of a summary, we shall outline the key points of each section.
To begin with, as "Points of PCB Layout", we have indicated the main issues addressed, from start to finish. These are brief summaries of the principal points, and so are presented here first.
Points of PCB Layout (Overall)
・When engaging in PCB layout (design), it is important to understand the current paths in the step-down converter.
・The sudden on-off of the currents in the switching operation of a switching regulator can adversely affect circuit operation and the like if measures are not taken in an appropriate PCB layout.
・In actual PCBs, there exist parasitic capacitances and inductances that do not appear on circuit diagrams
・Parasitic components may give rise to such problematic phenomena as ringing.
・PCB layout should be designed keeping such components in mind, aiming at optimal layout.
・It is a good idea to begin with placement of the input capacitor and diode.
・As an inviolable rule, the input capacitor and diode must always be placed on the same surface as the IC pins, and as close to the IC as possible.
・Parasitic inductance is a cause of noise, and so use of vias should be studied carefully. Places where current is switched require careful attention.
・Thermal vias are a means for causing heat to be conducted through a passage (hole) penetrating a circuit board to the opposite side, where it is dissipated.
・Thermal vias are placed directly below heating elements, or as close to them as possible.
・Inductors should be placed as close to ICs as possible.
・Copper foil areas should not be made broader than is necessary.
・Do not place the GND layer directly below an inductor. Signal lines should also be placed so as not to run under an inductor.
・Do not cause the wiring of inductor pins to approach each other.
・An output capacitor should be placed as close as possible to an inductor.
・In order to reduce the propagation of high-frequency noise, the GND of CIN should be placed 1 to 2 cm distant from the GND of CO.
・A feedback signal line from the output should be laid out away from the switching nodes. If the line picks up noise, errors and erroneous operation will result.
・Placing wiring on the bottom layer of the board through a via is another option.
・AGND and PGND must be separated. As a rule, PGND is laid out in the top layer, without interruption.
・If PGND is interrupted and connected on the rear surface using vias, losses and noise are worsened due to the via resistance and the effects of inductors.
・PGND should be connected to a common ground or a signal ground close to an output capacitor with little switching noise.
・Understand the basic construction of a printed circuit board.
・The resistance of copper foil layers appears as a voltage drop, and is dependent on temperature.
・The inductance of copper foil layers can in some cases generate high voltages, so care should be exercised
・Shortening wiring lengths is effective for reducing inductance.
・Corner wiring should describe arcs, so that the change in wiring impedance is lessened and noise is not induced.
・Measures to deal with noise terminal voltage (conducted emissions) include beads and pi filters selected according to the noise frequencies.
・To cope with noise electric field intensity (radiated noise), the placement of the input capacitor is optimized, and the steepness of the switching waveform is adjusted.
・A snubber can reduce ringing in switching, but there is a trade-off with increased losses.
・When a bootstrap resistor is added, rising-edge noise can be reduced, but MOSFET switching losses increase.
・By adding a resistor at the gate, both rising and falling noise can be reduced, but MOSFET losses are increased. Moreover, this resistor cannot be inserted when an IC with an internal MOSFET is used.
With this we conclude our discussion of "Board Layout of DC/DC Converters".