PCB layout for step-up DC/DC converters has been explained over the course of 11 articles. This final article in the series summarizes the key points and provides links to the respective articles.
PCB Layout of a Step-Up DC/DC Converter
・When designing a switching power supply, similarly to the circuit design, the PCB layout design is also important.
・In this chapter, the PCB layout of step-up DC/DC converters is explained.
・In PCB layout design, it is important that current paths in the circuit and the properties of currents flowing in these paths be understood (and not only in step-up DC/DC converters).
・The system of current differences when the switching transistor is on and is off is extremely important for board layout, and demands the utmost attention.
・The PCB layout is designed based on current paths in the circuit and the properties of the flowing currents.
・CIBYPASS must always be placed on the same surface as the IC, and should be positioned as close to the IC input pin as possible.
・When CIBYPASS is positioned suitably, CIN may be placed about 2 cm from the IC, and may also be mounted on the opposite side.
・A single ceramic capacitor can be used in place of both CIN and CIBYPASS if both supply of large currents and rapid response to high-frequency switching currents can be secured.
・If the output current is small, only a comparatively small value is needed for the output capacitor. Hence a single ceramic capacitor can be used as both the output capacitor and as a high-frequency decoupling capacitor.
・The freewheel diode is positioned near the IC and the output capacitor on the same surface.
・If the wiring of the node connecting the diode and the switching MOSFET is long, high-frequency spike noise induced by the wiring inductance is superposed on the output.
・A snubber circuit can be used to deal with spike noise, but it should be recognized that losses occur in the snubber circuit.
・The inductor should be placed close to the switching MOSFET Q2, and the area of the copper foil wiring should not be made larger than necessary.
・As a guideline for determining the wiring width, the current rating should be considered, and the width should be chosen with a margin included.
・The ground layer must not be located directly below the inductor. In addition to the ground layer, signal lines should likewise not be positioned below the inductor.
・If wiring directly below the inductor cannot be avoided, an inductor with a closed magnetic circuit structure and minimal leakage of magnetic lines of force should be used.
・The distance between inductor terminals should not be shortened.
・When PCB mounting alone results in inadequate heat dissipation, thermal vias are provided to conduct heat to the opposite side of the board and reduce thermal resistance.
・In order to improve thermal conductivity, it is recommended that thermal vias have a small inner diameter of approx. 0.3 mm, enabling filling with plating.
・If the hole diameter is too large, solder suction problems occur in the reflow soldering process.
・The thermal via interval should be about 1.2 mm, with the vias positioned directly below the heat sinks on the bottom surfaces of IC packages.
・If thermal vias below IC bottom-surface heat sinks are by themselves inadequate for heat dissipation, thermal vias should also be provided on the periphery of the ICs.
・When an IC bottom-surface heat sink is at ground potential, a large-area copper foil trace can be used without adverse EMI effects.
・Feedback path wiring has high impedance and picks up noise easily.
・When feedback path wiring picks up noise, errors may occur in the output voltage, and operation may become unstable.
・The four matters noted in the text require attention when laying out wiring for feedback paths.
・AGND and PGND must be separated.
・As a basic rule, PGND should be positioned in the top layer without being divided.
・If PGND is divided and connected on the rear surface through vias, losses and noise are worsened due to the via resistance and inductance.
・When ground planes are positioned in inner layers and on the rear surface of a multiplayer board, care must be exercised when connecting the PGND to the input or to diodes at which there is much high-frequency switching noise.
・The top-layer PGND and an inner-layer PGND plane should be connected through numerous vias to reduce the impedance, in order to alleviate DC losses.
・The PGND should be connected to a common ground or a signal ground at the PGND near the output capacitor, where high-frequency noise is low, and must not be connected at the PGND near the input or diodes, where noise levels are higher.
・Points to be aware of in PCB layout are basically the same for diode rectification and for synchronous rectification.
・The resistance of copper foil appears as a drop in voltage, and depends on the temperature.
・The inductance of copper foil can result in high voltages under some circumstances, thus requiring caution.
・Shortening wiring lengths is effective to reduce inductances.
・Corner wiring should describe arc shapes so that the change in wiring impedance is smaller, and noise is not generated.